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1. 发明授权

US08570887B2 Analog bias control for packet communication systems 有权
标题翻译：分组通信系统的模拟偏置控制
公开(公告)号：US08570887B2
公开(公告)日：2013-10-29
申请号：US12944031
申请日：2010-11-11
申请人： Thomas B. Cho , Li Lin , Mao Yu , Atul Salhotra
发明人： Thomas B. Cho , Li Lin , Mao Yu , Atul Salhotra
IPC分类号： G01R31/08
CPC分类号： H04L27/0002 , H03F1/0272 , H03G3/3068
摘要： Apparatus having corresponding methods and non-transitory computer-readable media comprise an amplifier configured to amplify signals according to a bias current, wherein the signals represent packets of data; a packet module configured to recover the packets of data from the signals amplified by the amplifier; and a control module configured to control the bias current according to one or more characteristics of the packets of data.
摘要翻译：具有相应方法和非瞬时计算机可读介质的装置包括放大器，其经配置以根据偏置电流放大信号，其中所述信号表示数据分组; 分组模块，被配置为从放大器放大的信号中恢复数据分组; 以及控制模块，被配置为根据所述数据分组的一个或多个特性来控制所述偏置电流。

2. 发明授权

US08536874B1 Integrated circuit voltage domain detection system and associated methodology 有权
标题翻译：集成电路电压域检测系统及相关方法
公开(公告)号：US08536874B1
公开(公告)日：2013-09-17
申请号：US11407417
申请日：2006-04-20
申请人： Thomas B. Cho , Wai-Tat Wong
发明人： Thomas B. Cho , Wai-Tat Wong
IPC分类号： G01R31/08
CPC分类号： G01R19/16552
摘要： A voltage sensing module for an integrated circuit (IC) that supports operation at a plurality of different voltage levels includes a voltage generation module that generates first and second voltages based on an operating voltage level of the IC. A comparing module receives the first and second voltages and generates a voltage determination signal based on the first and second signals. The voltage determination signal selectively configures an input/output I/O pad of the IC.
摘要翻译：用于支持在多个不同电压电平下操作的集成电路（IC）的电压感测模块包括基于IC的工作电压电平产生第一和第二电压的电压产生模块。比较模块接收第一和第二电压，并且基于第一和第二信号产生电压确定信号。电压确定信号选择性地配置IC的输入/输出I / O焊盘。

3. 发明授权

US07397412B1 Low power analog to digital converter 有权
标题翻译：低功耗模数转换器
公开(公告)号：US07397412B1
公开(公告)日：2008-07-08
申请号：US11486906
申请日：2006-07-14
申请人： Thomas B. Cho
发明人： Thomas B. Cho
IPC分类号： H03M1/38
CPC分类号： H03M1/002 , H03M1/123 , H03M1/164
摘要： A pipelined analog to digital converter comprises N stages, wherein N is an integer greater than one. A sample and integrate circuit communicates with at least two stages of the N stages. The sample and integrate circuit selectively samples a first voltage input to one of the at least two stages while integrating a difference between a sampled second voltage input of another one of the at least two stages and a second reference voltage to generate a second residue. The sample and integrate circuit selectively integrates a difference between the sampled first voltage and a first reference voltage to generate a first residue while sampling a second voltage input.
摘要翻译：流水线模数转换器包括N级，其中N是大于1的整数。采样和集成电路与N级的至少两级进行通信。采样和积分电路选择性地将第一电压输入采样到至少两个级中的一个级，同时积分至少两级中的另一级的采样的第二电压输入与第二参考电压之间的差以产生第二残差。采样和积分电路选择性地将采样的第一电压和第一参考电压之间的差异积分，以在对第二电压输入进行采样时产生第一残余。

4. 发明授权

US4891308A Photographic film antistatic backing layer with auxiliary layer having improved properties 失效
标题翻译：具有改善性能的辅助层的摄影胶片抗静电背衬层
公开(公告)号：US4891308A
公开(公告)日：1990-01-02
申请号：US344974
申请日：1989-04-14
申请人： Thomas B. Cho
发明人： Thomas B. Cho
IPC分类号： G03C1/89
CPC分类号： G03C1/7614 , G03C1/89 , G03C2001/7628
摘要： As part of a photographic film, a backing antistatic layer is coated at a pH of 3 to 12 with an auxiliary layer consisting essentially of at least one crosslinkable conductive polymer and a crosslinking agent for the conductive polymer dispersed in a binder, e.g., gelatin, to conduct the antistatic properties from the antistatic underlayer to the surface of the backing layer. The crosslinkable conductive polymer and crosslinking agent can be present in separate layers on the backing layer. The film is useful in the areas of graphic arts, printing, medical and information systems.
摘要翻译：作为照相胶片的一部分，背衬抗静电层的涂层厚度为3至12，其辅助层主要由至少一种可交联的导电聚合物和分散在粘合剂中的导电聚合物的交联剂组成，例如明胶，以将抗静电性能从抗静电底层传导到背衬层的表面。可交联的导电聚合物和交联剂可以存在于背衬层上的分开的层中。这部电影在图形艺术，印刷，医疗和信息系统领域很有用。

5. 发明授权

US4585730A Antistatic backing layer with auxiliary layer for a silver halide element 失效
标题翻译：具有卤化银元件辅助层的抗静电背衬层
公开(公告)号：US4585730A
公开(公告)日：1986-04-29
申请号：US697378
申请日：1985-01-16
申请人： Thomas B. Cho
发明人： Thomas B. Cho
IPC分类号： B32B7/02 , B05D5/12 , B05D7/04 , C08J7/04 , G03C1/85 , H05F1/02 , G03C1/82
CPC分类号： G03C1/85 , Y10S430/162
摘要： As part of a photographic film, a backing layer is coated with an auxiliary layer designed to conduct antistatic properties from an antistatic underlayer to the surface of the backing.
摘要翻译：作为照相胶片的一部分，背衬层涂覆有辅助层，其被设计成将抗静电性能从抗静电底层传导到背衬表面。

6. 发明申请

US20110204724A1 Dual Output Direct Current (DC)-DC Regulator 有权
标题翻译：双输出直流（DC）-DC稳压器
公开(公告)号：US20110204724A1
公开(公告)日：2011-08-25
申请号：US13026938
申请日：2011-02-14
申请人： Ashutosh Verma , Shafiq M. Jamal , Thomas B. Cho , Sehat Sutardja
发明人： Ashutosh Verma , Shafiq M. Jamal , Thomas B. Cho , Sehat Sutardja
IPC分类号： H02M3/06
CPC分类号： H02M3/07 , H02M2001/009
摘要： An apparatus includes a first switch coupled to a first voltage reference and a second switch coupled to a second voltage reference. A third switch is coupled to a first terminal of a first capacitor and a first terminal of a second capacitor. A fourth switch is coupled to a second terminal of the first capacitor and the first terminal of the second capacitor. A fifth switch is coupled to the second terminal of the first capacitor and a first terminal of a third capacitor. A sixth switch is coupled to the first terminal of the first capacitor and the first terminal of the third capacitor. The first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch are controlled to maintain a first voltage level at a first output and a second voltage level at a second output.
摘要翻译：一种装置包括耦合到第一电压基准的第一开关和耦合到第二电压基准的第二开关。第三开关耦合到第一电容器的第一端子和第二电容器的第一端子。第四开关耦合到第一电容器的第二端子和第二电容器的第一端子。第五开关耦合到第一电容器的第二端子和第三电容器的第一端子。第六开关耦合到第一电容器的第一端子和第三电容器的第一端子。控制第一开关，第二开关，第三开关，第四开关，第五开关和第六开关，以将第一电压电平维持在第一输出，第二电压电平维持在第二输出。

7. 发明授权

US07768438B1 Low power analog to digital converter 有权
标题翻译：低功耗模数转换器
公开(公告)号：US07768438B1
公开(公告)日：2010-08-03
申请号：US12558830
申请日：2009-09-14
申请人： Thomas B. Cho
发明人： Thomas B. Cho
IPC分类号： H03M1/12
CPC分类号： H03M1/002 , H03M1/123 , H03M1/164
摘要： A sample and integrate circuit includes first and second switching devices. A first terminal of the first switching device communicates with a first input voltage when the first switching device is in the second state. The first terminal of the first switching device communicates with a first voltage reference when the first switching device is in the first state. A first capacitance communicates with the second terminal of the first switching device. A first terminal of the second switching device communicates with a second input voltage when the second switching device is in the first state. The first terminal of the second switching device communicates with a second voltage reference when the second switching device is in the second state. A first input of an amplifier communicates with the first capacitance and a second capacitance. A second input of the amplifier communicates with a third capacitance and a fourth capacitance.
摘要翻译：采样和集成电路包括第一和第二开关装置。当第一开关装置处于第二状态时，第一开关装置的第一端子与第一输入电压通信。当第一开关装置处于第一状态时，第一开关装置的第一端子与第一电压基准通信。第一电容与第一开关器件的第二端子连通。当第二开关装置处于第一状态时，第二开关装置的第一端与第二输入电压通信。当第二开关装置处于第二状态时，第二开关装置的第一端与第二电压基准通信。放大器的第一输入与第一电容和第二电容进行通信。放大器的第二输入端与第三电容和第四电容器通信。

8. 发明授权

US07750706B1 Circuits, architectures, apparatuses, systems, and methods for low voltage clock delay generation 失效
标题翻译：用于低电压时钟延迟生成的电路，架构，设备，系统和方法
公开(公告)号：US07750706B1
公开(公告)日：2010-07-06
申请号：US11879080
申请日：2007-07-13
申请人： Thomas B. Cho , Xiaoyue Wang
发明人： Thomas B. Cho , Xiaoyue Wang
IPC分类号： H03K3/289
CPC分类号： H03K5/13 , H03K2005/00026 , H03K2005/00097 , H03L7/0812
摘要： Circuits, systems, and methods for generating a delayed clock signal. The circuit generally includes a first ramp generator configured to produce a first ramp signal in response to a reference clock signal, a first comparison circuit configured to compare the first ramp signal to a first threshold value in response to the reference clock signal to produce a comparison signal, a second ramp generator configured to produce a second ramp signal in response to the comparison signal, and a second comparison circuit configured to compare the second ramp signal to a second threshold value to produce the delayed clock signal.
摘要翻译：用于产生延迟时钟信号的电路，系统和方法。电路通常包括第一斜坡发生器，其被配置为响应于参考时钟信号产生第一斜坡信号，第一比较电路被配置为响应于参考时钟信号将第一斜坡信号与第一阈值进行比较以产生比较信号，第二斜坡发生器，被配置为响应于所述比较信号产生第二斜坡信号;以及第二比较电路，被配置为将所述第二斜坡信号与第二阈值进行比较以产生所述延迟的时钟信号。

9. 发明授权

US07081775B2 Bias technique for operating point control in multistage circuits 有权
公开(公告)号：US07081775B2
公开(公告)日：2006-07-25
申请号：US10379132
申请日：2003-03-03
申请人： Christopher D. Nilson , Thomas B. Cho
发明人： Christopher D. Nilson , Thomas B. Cho
IPC分类号： H03R5/22
CPC分类号： G05F3/242
摘要： A multistage analog circuit for independently controlling a bias current in each stage of the multistage analog circuit having an input stage, an intermediate stage, and an output stage, includes a first current source which controls the input stage of the circuit, a second current source which controls the intermediate stage of the circuit, and a third current source which controls the output stage of the circuit. The bias current in each stage of the circuit is set by the first, second, and third current sources. An output voltage of the circuit is capable of remaining the same when the first current source is changed to affect an input transconductance of the circuit.

10. 发明授权

US07065327B1 Single-chip CMOS direct-conversion transceiver 有权
标题翻译：单芯片CMOS直接转换收发器
公开(公告)号：US07065327B1
公开(公告)日：2006-06-20
申请号：US09762720
申请日：1999-09-10
申请人： Donald Evan Macnally , Thomas B. Cho , Shahriar Rabii , Srenik Suresh Mehta , Christopher Donald Nilson , Michael Peter Mack , Laurence Marguerite Plouvier , Menno Marringa , Eric S. Dukatz
发明人： Donald Evan Macnally , Thomas B. Cho , Shahriar Rabii , Srenik Suresh Mehta , Christopher Donald Nilson , Michael Peter Mack , Laurence Marguerite Plouvier , Menno Marringa , Eric S. Dukatz
IPC分类号： H04B1/44
CPC分类号： H04B1/48
摘要： A single-chip CMOS direct conversion transceiver includes an RF circuit, a transmitter having a synthesizer, a receiver having a baseband filter, and a demodulator. The synthesizer is coupled to the RF circuit. The baseband filter is coupled to the RF circuit and the synthesizer. The demodulator is coupled to the baseband filter. The RF circuit, the synthesizer, the baseband filter, and the demodulator are arranged and configured in CMOS devices and provide a complete interface between an antenna and a voiceband codec.
摘要翻译：单芯片CMOS直接转换收发器包括RF电路，具有合成器的发射机，具有基带滤波器的接收机和解调器。合成器耦合到RF电路。基带滤波器耦合到RF电路和合成器。解调器耦合到基带滤波器。 RF电路，合成器，基带滤波器和解调器被布置和配置在CMOS器件中，并且在天线和语音频带编解码器之间提供完整的接口。

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