专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090282213A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20090282213A1
公开(公告)日：2009-11-12
申请号：US12505128
申请日：2009-07-17
申请人： Hiroshi TANAKA , Yohei Akita , Tetsuro Honmura , Fumio Arakawa , Takanobu Tsunoda
发明人： Hiroshi TANAKA , Yohei Akita , Tetsuro Honmura , Fumio Arakawa , Takanobu Tsunoda
IPC分类号： G06F15/80 , G06F9/02
CPC分类号： H03K19/17752 , H03K19/17728 , H03K19/17736 , H03K19/17744 , H03K19/1776
摘要： A basic cell capable of a fixed operating frequency regardless of the configuration information, which is also capable of effectively utilizing the arithmetic logic circuit within the cell in a LSI semiconductor integrated circuit, is capable of dynamic changes in configuration information. The circuit has an input switch ISW connected to multiple data input nodes, an output switch OSW connected to multiple data output nodes, a first data path containing an arithmetic logic circuit ALU and a result storage flip-flop CFF0 between the input switch ISW and output switch OSW. The second data path containing a data transfer flip-flop between an input switch ISW and an output switch OSW, and the result storage flip-flop CFF stores the calculated result data from the arithmetic logic circuit ALU, and the data transfer flip-flop holds data input from any of the multiple data input nodes.
摘要翻译：能够具有固定工作频率的基本单元能够动态地改变配置信息，而与能够有效地利用LSI半导体集成电路中的单元内的算术逻辑电路的配置信息无关。该电路具有连接到多个数据输入节点的输入开关ISW，连接到多个数据输出节点的输出开关OSW，在输入开关ISW和输出端之间包含算术逻辑电路ALU和结果存储触发器CFF0的第一数据路径切换OSW。包含输入开关ISW和输出开关OSW之间的数据传输触发器的第二数据路径，结果存储触发器CFF存储来自算术逻辑电路ALU的计算结果数据，并且数据传送触发器保持从多个数据输入节点中的任何一个输入的数据。

2. 发明授权

US07406643B2 Semiconductor integrated circuit device, method of manufacturing the device, and computer readable medium 失效
标题翻译：半导体集成电路器件，该器件的制造方法以及计算机可读介质
公开(公告)号：US07406643B2
公开(公告)日：2008-07-29
申请号：US10860051
申请日：2004-06-04
申请人： Kenichi Osada , Koichiro Ishibashi , Kazuo Yano , Tetsuro Honmura
发明人： Kenichi Osada , Koichiro Ishibashi , Kazuo Yano , Tetsuro Honmura
IPC分类号： G01R31/28 , G11C7/00
CPC分类号： G11C29/028 , G11C15/00 , G11C29/50 , G11C29/50012 , G11C2029/0403
摘要： A semiconductor integrated circuit device which guarantees the characteristics of writing to and reading from the built-in memory even when the manufacturing process conditions are varied, a method of manufacturing the device, and a medium for storing a processing procedure for deciding the number of delay circuits built in the device used for designing. The semiconductor integrated circuit device is provided with a cache memory which includes a BIST circuit composed of a pattern generator, a pattern comparator, an output register, a register controlled by a register control a register write signal; a variable delay circuit controlled by the register; word lines, and a sense amplifier enable signal line. The timing for enabling the sense amplifier is changed and the memory is measured by a BIST circuit at the timing, thereby deciding the optimal timing.
摘要翻译：一种半导体集成电路器件，即使在制造工艺条件变化时也保证写入和读取内部存储器的特性，制造器件的方法以及用于存储用于确定延迟次数的处理过程的介质电路内置在用于设计的设备中。半导体集成电路器件具有高速缓冲存储器，其包括由模式发生器，模式比较器，输出寄存器，由寄存器控制的寄存器控制寄存器写入信号组成的BIST电路; 由寄存器控制的可变延迟电路; 字线和读出放大器使能信号线。改变启用读出放大器的定时，并且通过BIST电路在定时测量存储器，由此决定最佳定时。

3. 发明授权

US5249276A Address translation apparatus having a memory access privilege check capability data which uses mask data to select bit positions of priviledge 失效
标题翻译：地址转换装置具有使用掩码数据来选择特权位的位置的存储器访问特权检查能力数据
公开(公告)号：US5249276A
公开(公告)日：1993-09-28
申请号：US208493
申请日：1988-06-20
申请人： Tetsuro Honmura , Katsuaki Takagi , Shunpei Kawasaki , Nobutaka Amano , Kimio Ooe
发明人： Tetsuro Honmura , Katsuaki Takagi , Shunpei Kawasaki , Nobutaka Amano , Kimio Ooe
IPC分类号： G06F12/10
CPC分类号： G06F12/1027
摘要： An address translation apparatus which includes a memory for storing a plurality of physical addresses, and a content addressable memory unit which stores a plurality of signal pairs that correspond to the plurality of physical addresses, each of the signal paris includes a logical address that corresponds to one of the plurality of physical addresses and memory protection level data that indicates a memory protection level allocated to a memory position of the one of the physical addresses. The content addressable memory unit includes apparatus for searching a signal pair that has a logical address in coincident with a logical address being subjected to address translation and comparing memory protection level data to comparative data at a bit position which is indicated to be the bit position to be searched by mask data, in response to the logical address translation. The mask data instructs whether the bits of the stored memory protection level data are to be searched, wherein mask data is determined depending upon a memory access privilege level allocated to a program that requests address translation, and whether comparative data are to be compared with the stored memory protection level data. The content addressable memory further includes apparatus for instructing the memory to produce a physical address that corresponds to the detected signal pair.
摘要翻译：一种包括用于存储多个物理地址的存储器的地址转换装置，以及存储对应于多个物理地址的多个信号对的内容可寻址存储单元，每个信号码包括对应于多个物理地址和存储器保护级别数据中的一个指示分配给物理地址之一的存储器位置的存储器保护级别。内容可寻址存储器单元包括用于搜索具有与经受地址转换的逻辑地址一致的逻辑地址的信号对的装置，并将存储器保护级别数据与指示为位位置的位位置的比较数据进行比较通过掩码数据进行搜索，以响应逻辑地址转换。掩模数据指示是否搜索所存储的存储器保护级别数据的位，其中根据分配给请求地址转换的程序的存储器访问权限级别确定掩码数据，以及比较数据是否与存储内存保护级数据。内容可寻址存储器还包括用于指示存储器产生对应于检测到的信号对的物理地址的装置。

4. 发明授权

US07568084B2 Semiconductor integrated circuit including multiple basic cells formed in arrays 失效
标题翻译：半导体集成电路包括以阵列形成的多个基本单元
公开(公告)号：US07568084B2
公开(公告)日：2009-07-28
申请号：US10886616
申请日：2004-07-09
申请人： Hiroshi Tanaka , Yohei Akita , Tetsuro Honmura , Fumio Arakawa , Takanobu Tsunoda
发明人： Hiroshi Tanaka , Yohei Akita , Tetsuro Honmura , Fumio Arakawa , Takanobu Tsunoda
IPC分类号： G06F15/00
CPC分类号： H03K19/17752 , H03K19/17728 , H03K19/17736 , H03K19/17744 , H03K19/1776
摘要： A basic cell capable of a fixed operating frequency regardless of the configuration information, which is also capable of effectively utilizing the arithmetic logic circuit within the cell in a LSI semiconductor integrated circuit, is capable of dynamic changes in configuration information. The circuit has an input switch ISW connected to multiple data input nodes, an output switch OSW connected to multiple data output nodes, a first data path containing an arithmetic logic circuit ALU and a result storage flip-flop CFF0 between the input switch ISW and output switch OSW. The second data path containing a data transfer flip-flop between an input switch ISW and an output switch OSW, and the result storage flip-flop CFF stores the calculated result data from the arithmetic logic circuit ALU, and the data transfer flip-flop holds data input from any of the multiple data input nodes.
摘要翻译：能够具有固定工作频率的基本单元能够动态地改变配置信息，而与能够有效地利用LSI半导体集成电路中的单元内的算术逻辑电路的配置信息无关。该电路具有连接到多个数据输入节点的输入开关ISW，连接到多个数据输出节点的输出开关OSW，在输入开关ISW和输出端之间包含算术逻辑电路ALU和结果存储触发器CFF0的第一数据路径切换OSW。包含输入开关ISW和输出开关OSW之间的数据传输触发器的第二数据路径，结果存储触发器CFF存储来自算术逻辑电路ALU的计算结果数据，并且数据传送触发器保持从多个数据输入节点中的任何一个输入的数据。

5. 发明申请

US20050015572A1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US20050015572A1
公开(公告)日：2005-01-20
申请号：US10886616
申请日：2004-07-09
申请人： Hiroshi Tanaka , Yohei Akita , Tetsuro Honmura , Fumio Arakawa , Takanobu Tsunoda
发明人： Hiroshi Tanaka , Yohei Akita , Tetsuro Honmura , Fumio Arakawa , Takanobu Tsunoda
IPC分类号： H01L21/82 , G06F15/80 , H03K19/177 , G06F15/00
CPC分类号： H03K19/17752 , H03K19/17728 , H03K19/17736 , H03K19/17744 , H03K19/1776
摘要： A basic cell capable of a fixed operating frequency regardless of the configuration information, which is also capable of effectively utilizing the arithmetic logic circuit within the cell in a LSI semiconductor integrated circuit, is capable of dynamic changes in configuration information. The circuit has an input switch ISW connected to multiple data input nodes, an output switch OSW connected to multiple data output nodes, a first data path containing an arithmetic logic circuit ALU and a result storage flip-flop CFF0 between the input switch ISW and output switch OSW. The second data path containing a data transfer flip-flop between an input switch ISW and an output switch OSW, and the result storage flip-flop CFF stores the calculated result data from the arithmetic logic circuit ALU, and the data transfer flip-flop holds data input from any of the multiple data input nodes.
摘要翻译：能够具有固定工作频率的基本单元能够动态地改变配置信息，而与能够有效地利用LSI半导体集成电路中的单元内的算术逻辑电路的配置信息无关。该电路具有连接到多个数据输入节点的输入开关ISW，连接到多个数据输出节点的输出开关OSW，在输入开关ISW和输出端之间包含算术逻辑电路ALU和结果存储触发器CFF0的第一数据路径切换OSW。包含输入开关ISW和输出开关OSW之间的数据传输触发器的第二数据路径，结果存储触发器CFF存储来自算术逻辑电路ALU的计算结果数据，并且数据传送触发器保持从多个数据输入节点中的任何一个输入的数据。

6. 发明授权

US06782499B2 Semiconductor integrated circuit device, method of manufacturing the device, and computer readable medium 失效
标题翻译：半导体集成电路器件，该器件的制造方法以及计算机可读介质
公开(公告)号：US06782499B2
公开(公告)日：2004-08-24
申请号：US10285573
申请日：2002-11-01
申请人： Kenichi Osada , Koichiro Ishibashi , Kazuo Yano , Tetsuro Honmura
发明人： Kenichi Osada , Koichiro Ishibashi , Kazuo Yano , Tetsuro Honmura
IPC分类号： G01R3128
CPC分类号： G11C29/028 , G11C15/00 , G11C29/50 , G11C29/50012 , G11C2029/0403
摘要： A semiconductor integrated circuit device supplied as an IP (Intellectual Property), etc., a method of manufacturing the device, and a medium for storing a processing procedure for deciding the number of delay circuits built in the device used for designing, more particularly to a semiconductor integrated circuit device which guarantees the characteristics of writing into and reading from the built-in memory even when the manufacturing process conditions are varied. The semiconductor integrated circuit device is provided with a cache memory which includes a BIST circuit composed of a pattern generator, a pattern comparator, and an output register; a register controlled by a register control signal and a register write signal; a variable delay circuit controlled by the register; word lines, and a sense amplifier enable signal line. The timing for enabling the sense amplifier is changed and the memory is measured by a BIST circuit at the timing, thereby deciding the optimal timing.
摘要翻译：一种半导体集成电路器件，即使在制造工艺条件变化时也保证写入和读取内置存储器的特性。半导体集成电路装置具有高速缓冲存储器，其包括由图案发生器，图案比较器和输出寄存器构成的BIST电路; 由寄存器控制信号和寄存器写入信号控制的寄存器; 由寄存器控制的可变延迟电路; 字线和读出放大器使能信号线。改变启用读出放大器的定时，并且通过BIST电路在定时测量存储器，由此决定最佳定时。

7. 发明授权

US06496952B1 Semiconductor integrated circuit device, method of manufacturing the device, and computer readable medium 有权
标题翻译：半导体集成电路器件，该器件的制造方法以及计算机可读介质
公开(公告)号：US06496952B1
公开(公告)日：2002-12-17
申请号：US09399330
申请日：1999-09-20
申请人： Kenichi Osada , Koichiro Ishibashi , Kazuo Yano , Tetsuro Honmura
发明人： Kenichi Osada , Koichiro Ishibashi , Kazuo Yano , Tetsuro Honmura
IPC分类号： G01R3128
CPC分类号： G11C29/028 , G11C15/00 , G11C29/50 , G11C29/50012 , G11C2029/0403
摘要： A semiconductor integrated circuit device, a method of manufacturing the device, and a medium for storing a processing procedure for deciding the number of delay circuits built in the device used for designing are disclosed. More particularly, a semiconductor integrated circuit device which guarantees the characteristics of writing into and reading from the built-in memory even when the manufacturing process conditions are varied is obtained. The semiconductor integrated circuit device is provided with a cache memory which includes a BIST circuit composed of a pattern generator, a pattern comparator, and an output register; a register controlled by a register control signal and a register write signal; a variable delay circuit controlled by the register; word lines, and a sense amplifier enable signal line. The timing for enabling the sense amplifier is changed and the memory is measured by the BIST, thereby deciding the optimal timing.
摘要翻译：公开了一种半导体集成电路器件，该器件的制造方法以及用于存储用于确定用于设计的器件中构建的延迟电路的数量的处理过程的介质。更具体地说，即使在制造工艺条件变化的情况下，也能够确保写入和读出内置存储器的特性的半导体集成电路器件。半导体集成电路装置具有高速缓冲存储器，其包括由图案发生器，图案比较器和输出寄存器构成的BIST电路; 由寄存器控制信号和寄存器写入信号控制的寄存器; 由寄存器控制的可变延迟电路; 字线和读出放大器使能信号线。改变启用读出放大器的定时，并通过BIST测量存储器，从而确定最佳定时。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式