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    • 2. 发明授权
    • Digital clock modulator
    • 数字时钟调制器
    • US07436235B2
    • 2008-10-14
    • US10909939
    • 2004-08-02
    • Tapas Nandy
    • Tapas Nandy
    • G06F1/04
    • H03K5/133H03K5/1252H04B15/04H04B2215/064H04B2215/067
    • A digital clock modulator provides a smoothly modulated clock period to reduce emitted electro-magnetic radiation (EMR). The digital clock modulator includes a plurality of delay elements connected in series and receiving as an input an unmodulated clock signal. A multiplexer receives inputs from unequally spaced taps between the delay elements. A control block provides selection inputs to the multiplexer, and receives the unmodulated clock signal from the delay elements. The delay elements include a last delay element providing the unmodulated clock signal to the control block. The last delay element has a predetermined delay for ensuring that the delay elements and related signal paths are in a same stable state before control to the multiplexer changes.
    • 数字时钟调制器提供平滑调制的时钟周期以减少发射的电磁辐射(EMR)。 数字时钟调制器包括串联连接的多个延迟元件,作为未调制的时钟信号作为输入。 多路复用器从延迟元件之间的不等间距的抽​​头接收输入。 控制块向多路复用器提供选择输入,并从延迟元件接收未调制的时钟信号。 延迟元件包括向控制块提供未调制时钟信号的最后延迟元件。 最后一个延迟元件具有预定的延迟,用于确保延迟元件和相关信号路径在对多路复用器的控制改变之前处于相同的稳定状态。
    • 3. 发明申请
    • HDMI RECEIVER
    • HDMI接收器
    • US20120169438A1
    • 2012-07-05
    • US12980878
    • 2010-12-29
    • Tapas NANDYNitin GUPTA
    • Tapas NANDYNitin GUPTA
    • H03H7/24H03L5/00
    • H03F3/45928H03F3/45475H03F2200/294H03F2200/411H03F2203/45544H03F2203/45594H03F2203/45596H03F2203/45631H03F2203/45702
    • An embodiment of a transmitter includes an amplifier having first and second differential output nodes, a first supply node, a first pull-up impedance having a first node coupled to the first differential output node and having a second node coupled to the supply node, and a second pull-up impedance having a first node coupled to the second differential output node and having a second node coupled to the supply node. An embodiment of a receiver includes an amplifier having first and second differential input nodes, a first supply node, a first pull-up impedance having a first node coupled to the first differential input node and having a second node coupled to the supply node, and a second pull-up impedance having a first node coupled to the second differential input node and having a second node coupled to the supply node. In an embodiment, the transmitter and receiver are capacitively coupled to one another.
    • 发射机的实施例包括具有第一和第二差分输出节点的放大器,第一供电节点,第一上拉阻抗,其具有耦合到第一差分输出节点的第一节点并且具有耦合到供电节点的第二节点,以及 第二上拉阻抗,其具有耦合到所述第二差分输出节点并且具有耦合到所述电源节点的第二节点的第一节点。 接收机的实施例包括具有第一和第二差分输入节点的放大器,第一供电节点,第一上拉阻抗,其具有耦合到第一差分输入节点的第一节点并且具有耦合到供应节点的第二节点,以及 第二上拉阻抗,其具有耦合到所述第二差分输入节点并具有耦合到所述电源节点的第二节点的第一节点。 在一个实施例中,发射机和接收机彼此电容耦合。