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1. 发明申请

US20120048355A1 SEMICONDUCTOR DEVICE MODULE PACKAGE STRUCTURE AND SERIES CONNECTION METHOD THEREOF 审中-公开
标题翻译：半导体器件模块封装结构及其连接方法
公开(公告)号：US20120048355A1
公开(公告)日：2012-03-01
申请号：US12982121
申请日：2010-12-30
申请人： Hsin-Hsin Hsieh , Chi-Shiung Hsi , Tao-Chih Chang
发明人： Hsin-Hsin Hsieh , Chi-Shiung Hsi , Tao-Chih Chang
IPC分类号： H01L31/0248 , H01L31/18
CPC分类号： H01L31/0504 , H01L31/02245 , H01L31/022458 , Y02E10/50
摘要： The invention provides a semiconductor device module package structure and a series connection method thereof. The semiconductor device module package structure includes a wafer having a plurality through holes. A doped layer covers a top surface of the first electrode, and inner sidewalls extending to a bottom surface of the first electrode. At least two first electrodes are disposed adjacent to each other and on opposite sides of the through holes. A second electrode covers the doped layer and the through holes. At least two insulating layer patterns overlap with the first and second electrodes. A second electrode conductive pattern is disposed on the second electrode. The second electrode conductive pattern is disposed between the insulating layer patterns, electrically connecting to the second electrode.
摘要翻译：本发明提供一种半导体器件模块封装结构及其串联方法。半导体器件模块封装结构包括具有多个通孔的晶片。掺杂层覆盖第一电极的顶表面，并且内侧壁延伸到第一电极的底表面。至少两个第一电极彼此相邻并且在通孔的相对侧布置。第二电极覆盖掺杂层和通孔。至少两个绝缘层图案与第一和第二电极重叠。第二电极导电图案设置在第二电极上。第二电极导电图案设置在电连接到第二电极的绝缘层图案之间。

2. 发明授权

US08093718B2 Chip structure and stacked structure of chips 有权
标题翻译：芯片结构和堆叠结构的芯片
公开(公告)号：US08093718B2
公开(公告)日：2012-01-10
申请号：US12110335
申请日：2008-04-27
申请人： Tao-Chih Chang
发明人： Tao-Chih Chang
IPC分类号： H01L23/24 , H01L23/48
CPC分类号： H01L24/13 , H01L21/76898 , H01L23/481 , H01L24/11 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/114 , H01L2224/116 , H01L2224/13021 , H01L2224/13022 , H01L2224/13099 , H01L2224/1319 , H01L2224/136 , H01L2224/16145 , H01L2224/81193 , H01L2224/81194 , H01L2224/81205 , H01L2224/81224 , H01L2224/81801 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/0001 , H01L2924/01006 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01059 , H01L2924/01079 , H01L2924/14 , H01L2924/351 , H01L2924/00014 , H01L2924/00
摘要： A chip structure and a stacked structure composed of the chip structures are provided. The chip structure has a substrate and at least one compliant contact. Furthermore, the chip structure may further have a redistribution layer for redistributing pads originally disposed around the substrate in a specific arrangement. The substrate has a first surface and a second surface. The compliant contact is embedded into the substrate and protrudes outside the first surface and the second surface of the substrate. The compliant contact has a compliant bump and a conductive layer encapsulating the compliant bump. The conductive layer can be connected with the redistribution layer. Two chip structures can be connected with each other through their compliant contacts or through their compliant contacts or redistribution layers.
摘要翻译：提供了由芯片结构构成的芯片结构和堆叠结构。芯片结构具有基底和至少一个顺应性接触。此外，芯片结构可以进一步具有再分配层，用于以特定布置重新分配初始设置在基板周围的焊盘。基板具有第一表面和第二表面。柔性接触件嵌入衬底中并突出到衬底的第一表面和第二表面之外。柔性接触件具有柔顺凸起和封装柔性凸起的导电层。导电层可以与再分布层连接。两个芯片结构可以通过它们的柔性触点或通过它们的柔性触点或再分布层彼此连接。

3. 发明申请

US20130168851A1 BUMP STRUCTURE AND ELECTRONIC PACKAGING SOLDER JOINT STRUCTURE AND FABRICATING METHOD THEREOF 有权
标题翻译：焊接结构和电子包装焊接接头结构及其制造方法
公开(公告)号：US20130168851A1
公开(公告)日：2013-07-04
申请号：US13484289
申请日：2012-05-31
申请人： Yu-Min Lin , Chau-Jie Zhan , Tao-Chih Chang
发明人： Yu-Min Lin , Chau-Jie Zhan , Tao-Chih Chang
IPC分类号： H01L23/498 , H01L21/28
CPC分类号： H01L24/13 , H01L23/49816 , H01L24/11 , H01L24/16 , H01L24/81 , H01L2224/0346 , H01L2224/0401 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05552 , H01L2224/05559 , H01L2224/05572 , H01L2224/05613 , H01L2224/05618 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/05684 , H01L2224/11462 , H01L2224/1147 , H01L2224/115 , H01L2224/11502 , H01L2224/11848 , H01L2224/11849 , H01L2224/11901 , H01L2224/11906 , H01L2224/13076 , H01L2224/13111 , H01L2224/13113 , H01L2224/13118 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13171 , H01L2224/13184 , H01L2224/16145 , H01L2224/16238 , H01L2224/16503 , H01L2224/16507 , H01L2224/81097 , H01L2224/81193 , H01L2224/8181 , H01L2924/00 , H01L2924/00012 , H01L2924/00014 , H01L2924/01014 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01322 , H01L2924/10253 , H01L2224/1146
摘要： A bump structure includes a substrate, a pad, an electrode and a protruding electrode. The pad is disposed on the substrate. The electrode is formed by a first metal material and disposed on the pad. The protruding electrode is formed by a second metal material and disposed on the electrode, wherein a cross-sectional area of the protruding electrode is less than a cross-sectional area of the electrode.
摘要翻译：凸块结构包括基板，焊盘，电极和突出电极。衬垫设置在衬底上。电极由第一金属材料形成并设置在焊盘上。突起电极由第二金属材料形成并设置在电极上，其中突出电极的横截面面积小于电极的横截面面积。

4. 发明申请

US20120091581A1 PACKAGE UNIT AND STACKING STRUCTURE THEREOF 有权
标题翻译：包装单元及其堆叠结构
公开(公告)号：US20120091581A1
公开(公告)日：2012-04-19
申请号：US13272771
申请日：2011-10-13
申请人： Yin-Po Hung , Tao-Chih Chang
发明人： Yin-Po Hung , Tao-Chih Chang
IPC分类号： H01L23/498
CPC分类号： H01L23/5389 , H01L24/13 , H01L24/24 , H01L24/32 , H01L24/82 , H01L24/92 , H01L25/105 , H01L2224/11849 , H01L2224/12105 , H01L2224/24011 , H01L2224/2405 , H01L2224/24226 , H01L2224/244 , H01L2224/245 , H01L2224/32225 , H01L2224/73267 , H01L2224/821 , H01L2224/82101 , H01L2224/82104 , H01L2224/82106 , H01L2224/82399 , H01L2224/8281 , H01L2224/82815 , H01L2224/8284 , H01L2224/8385 , H01L2224/92144 , H01L2225/1035 , H01L2225/1058 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/014 , H01L2924/0105 , H01L2924/06 , H01L2924/00
摘要： A package unit and a stacking structure thereof are provided. The package unit includes a substrate, a first patterned circuit layer, a first conductive pillar, a semiconductor element, an insulation layer, a second conductive pillar, a third conductive pillar, a second patterned circuit layer and a conductive bump. The first patterned circuit layer is disposed on a surface of the substrate. The first conductive pillar is deposited through the substrate. The semiconductor element is disposed on the substrate. The insulation layer covers the semiconductor element and the substrate. The second conductive pillar is deposited through the insulation layer. The third conductive pillar is deposited through the insulation layer. The second patterned circuit layer is disposed on the insulation layer. The conductive bump is disposed on the second patterned metal layer.
摘要翻译：提供封装单元及其堆叠结构。封装单元包括衬底，第一图案化电路层，第一导电柱，半导体元件，绝缘层，第二导电柱，第三导电柱，第二图案化电路层和导电凸块。第一图案化电路层设置在基板的表面上。第一导电柱通过衬底沉积。半导体元件设置在基板上。绝缘层覆盖半导体元件和基板。第二导电柱通过绝缘层沉积。第三导电柱通过绝缘层沉积。第二图案化电路层设置在绝缘层上。导电凸块设置在第二图案化金属层上。

5. 发明申请

US20100207266A1 CHIP PACKAGE STRUCTURE 审中-公开
标题翻译：芯片包装结构
公开(公告)号：US20100207266A1
公开(公告)日：2010-08-19
申请号：US12426967
申请日：2009-04-21
申请人： Tao-Chih Chang , Su-Tsai Lu , Chau-Jie Zhan , Chun-Chih Chuang , Jing-Ye Juang
发明人： Tao-Chih Chang , Su-Tsai Lu , Chau-Jie Zhan , Chun-Chih Chuang , Jing-Ye Juang
IPC分类号： H01L23/52
CPC分类号： H01L23/49811 , H01L21/563 , H01L23/3128 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/90 , H01L2224/05001 , H01L2224/05022 , H01L2224/0557 , H01L2224/05571 , H01L2224/13011 , H01L2224/13078 , H01L2224/13099 , H01L2224/131 , H01L2224/16225 , H01L2224/27013 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/81136 , H01L2224/81193 , H01L2224/81801 , H01L2224/83051 , H01L2224/83141 , H01L2224/83192 , H01L2224/83194 , H01L2224/83365 , H01L2224/83385 , H01L2224/838 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2924/351 , H01L2924/00 , H01L2924/00012 , H01L2224/05005 , H01L2224/05541
摘要： A chip package structure including a substrate, a plurality of electrodes, a chip, and a plurality of bumps is provided. Each of the electrodes has a bottom portion and an annular element, wherein the bottom portion is disposed on the substrate, the annular element is disposed on the bottom portion, and the bottom portion and the annular element define a containing recess. The chip is disposed above the substrate and has an active surface facing the substrate and a plurality of pads disposed on the active surface. The bumps are respectively disposed on the pads and respectively inserted into the containing recesses. The melting point of the electrodes is higher than that of the bumps. A chip package method is also provided.
摘要翻译：提供了包括基板，多个电极，芯片和多个凸块的芯片封装结构。每个电极具有底部和环形元件，其中底部设置在基板上，环形元件设置在底部上，底部和环形元件限定容纳凹部。芯片设置在基板上方并且具有面向基板的有源表面和设置在有源表面上的多个焊盘。凸块分别设置在焊盘上并分别插入容纳凹部中。电极的熔点高于凸块的熔点。还提供了芯片封装方法。

6. 发明授权

US09024441B2 Bump structure and electronic packaging solder joint structure and fabricating method thereof 有权
标题翻译：凸块结构和电子封装焊点结构及其制造方法
公开(公告)号：US09024441B2
公开(公告)日：2015-05-05
申请号：US13484289
申请日：2012-05-31
申请人： Yu-Min Lin , Chau-Jie Zhan , Tao-Chih Chang
发明人： Yu-Min Lin , Chau-Jie Zhan , Tao-Chih Chang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/00 , H01L23/498
CPC分类号： H01L24/13 , H01L23/49816 , H01L24/11 , H01L24/16 , H01L24/81 , H01L2224/0346 , H01L2224/0401 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05552 , H01L2224/05559 , H01L2224/05572 , H01L2224/05613 , H01L2224/05618 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/05684 , H01L2224/11462 , H01L2224/1147 , H01L2224/115 , H01L2224/11502 , H01L2224/11848 , H01L2224/11849 , H01L2224/11901 , H01L2224/11906 , H01L2224/13076 , H01L2224/13111 , H01L2224/13113 , H01L2224/13118 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13171 , H01L2224/13184 , H01L2224/16145 , H01L2224/16238 , H01L2224/16503 , H01L2224/16507 , H01L2224/81097 , H01L2224/81193 , H01L2224/8181 , H01L2924/00 , H01L2924/00012 , H01L2924/00014 , H01L2924/01014 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01322 , H01L2924/10253 , H01L2224/1146
摘要： A bump structure includes a substrate, a pad, an electrode and a protruding electrode. The pad is disposed on the substrate. The electrode is formed by a first metal material and disposed on the pad. The protruding electrode is formed by a second metal material and disposed on the electrode, wherein a cross-sectional area of the protruding electrode is less than a cross-sectional area of the electrode.
摘要翻译：凸块结构包括基板，焊盘，电极和突出电极。衬垫设置在衬底上。电极由第一金属材料形成并设置在焊盘上。突起电极由第二金属材料形成并设置在电极上，其中突出电极的横截面面积小于电极的横截面面积。

7. 发明授权

US08575754B2 Micro-bump structure 有权
标题翻译：微凸块结构
公开(公告)号：US08575754B2
公开(公告)日：2013-11-05
申请号：US12884188
申请日：2010-09-17
申请人： Tsung-Fu Tsai , Tao-Chih Chang , Chau-Jie Zhan
发明人： Tsung-Fu Tsai , Tao-Chih Chang , Chau-Jie Zhan
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05027 , H01L2224/05083 , H01L2224/05555 , H01L2224/05572 , H01L2224/05624 , H01L2224/1146 , H01L2224/1147 , H01L2224/13012 , H01L2224/1308 , H01L2224/13083 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/16 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/00014 , H01L2224/13099
摘要： A dished micro-bump structure with self-aligning functions is provided. The micro-bump structure takes advantage of the central concavity for achieving the accurate alignment with the corresponding micro-bumps.
摘要翻译：提供了具有自对准功能的碟形微凸块结构。微凸块结构利用中心凹面来实现与相应微凸块的准确对准。

8. 发明申请

US20090210055A1 ARTIFICIAL OPTIC NERVE NETWORK MODULE, ARTIFICIAL RETINA CHIP MODULE, AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：人工神经网络模块，人造革芯片模块及其制造方法
公开(公告)号：US20090210055A1
公开(公告)日：2009-08-20
申请号：US12211829
申请日：2008-09-17
申请人： Tao-Chih Chang , Min-Lin Lee
发明人： Tao-Chih Chang , Min-Lin Lee
IPC分类号： A61F2/14
CPC分类号： A61F9/08 , A61F2/141 , A61N1/36046
摘要： An artificial retina chip module including a signal processing chip, a first polymer bump layer, and a photodiode array chip is provided. The signal processing chip includes a plurality of first pad disposed on a surface thereof. The first polymer bump layer includes a plurality of polymer bumps insulated from one another. Each of the first polymer bumps is composed of a polymer material and a conductive layer coated on the polymer material. Each first polymer bump is embedded into the corresponding first pad and the signal processing chip, wherein one end of the first polymer bump protrudes from the first pad and the other end thereof protrudes from a back surface of the signal processing chip. The photodiode array chip is disposed at one side of the signal processing chip and is electrically connected to the signal processing chip through the first polymer bumps.
摘要翻译：提供了包括信号处理芯片，第一聚合物凸块层和光电二极管阵列芯片的人造视网膜芯片模块。信号处理芯片包括设置在其表面上的多个第一焊盘。第一聚合物凸块层包括彼此绝缘的多个聚合物凸块。每个第一聚合物凸块由聚合物材料和涂覆在聚合物材料上的导电层组成。每个第一聚合物凸块被嵌入到相应的第一焊盘和信号处理芯片中，其中第一聚合物凸块的一端从第一焊盘凸出并且另一端从信号处理芯片的后表面突出。光电二极管阵列芯片设置在信号处理芯片的一侧，并通过第一聚合物凸块与信号处理芯片电连接。

9. 发明申请

US20090152741A1 CHIP STRUCTURE AND FABRICATION PROCESS THEREOF AND FLIP CHIP PACKAGE STRUCTURE AND FABRICATION PROCESS THEREOF 审中-公开
标题翻译：其芯片结构及其制造工艺及其片式包装结构及其制造工艺
公开(公告)号：US20090152741A1
公开(公告)日：2009-06-18
申请号：US12192138
申请日：2008-08-15
申请人： Tao-Chih Chang , Chao-Kai Hsu
发明人： Tao-Chih Chang , Chao-Kai Hsu
IPC分类号： H01L21/768 , H01L23/488
CPC分类号： H01L25/0657 , G02B6/4214 , H01L21/563 , H01L23/3171 , H01L23/3192 , H01L23/481 , H01L23/49811 , H01L24/02 , H01L24/12 , H01L24/16 , H01L24/83 , H01L24/90 , H01L25/50 , H01L2224/0401 , H01L2224/13009 , H01L2224/13021 , H01L2224/13099 , H01L2224/16147 , H01L2224/16225 , H01L2224/16237 , H01L2224/2929 , H01L2224/293 , H01L2224/32225 , H01L2224/73104 , H01L2224/73204 , H01L2224/81141 , H01L2224/81191 , H01L2224/83191 , H01L2224/83194 , H01L2224/83365 , H01L2224/83385 , H01L2224/8383 , H01L2224/83851 , H01L2224/83856 , H01L2225/06513 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/00 , H01L2224/29075 , H01L2924/00014
摘要： A chip structure including a chip, a first dielectric layer and at least one first conductive layer is provided. The chip has an active surface, a backside and at least one bonding pad disposed on the active surface. The first dielectric layer is disposed on the active surface and has at least one first opening, wherein the first opening correspondingly exposes the bonding pad. The first conductive layer covers an inner wall of the first opening and the bonding pad so as to form a concave structure in the first opening. When the chip structure is bonded to a substrate, the solder bump of the substrate is inlaid into the concave structure of the chip. Moreover, a fabrication process of the chip structure, a flip chip package structure and a fabrication process thereof, a package structure of a light emitting/receiving device and a chip stacked structure are also provided.
摘要翻译：提供了包括芯片，第一介电层和至少一个第一导电层的芯片结构。芯片具有活性表面，背面以及设置在活性表面上的至少一个粘结垫。第一电介质层设置在有源表面上并且具有至少一个第一开口，其中第一开口相应地暴露接合焊盘。第一导电层覆盖第一开口的内壁和接合焊盘，以便在第一开口中形成凹形结构。当芯片结构结合到基板上时，衬底的焊料凸块镶嵌在芯片的凹形结构中。此外，还提供了芯片结构的制造工艺，倒装芯片封装结构及其制造工艺，发光/接收装置的封装结构和芯片堆叠结构。

10. 发明申请

US20090121348A1 CHIP STRUCTURE AND PROCESS THEREOF AND STACKED STRUCTURE OF CHIPS AND PROCESS THEREOF 有权
标题翻译：芯片结构及其工艺及其结构及其加工过程
公开(公告)号：US20090121348A1
公开(公告)日：2009-05-14
申请号：US12110335
申请日：2008-04-27
申请人： Tao-Chih Chang
发明人： Tao-Chih Chang
IPC分类号： H01L23/48 , H01L21/60 , H01L21/44
CPC分类号： H01L24/13 , H01L21/76898 , H01L23/481 , H01L24/11 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/114 , H01L2224/116 , H01L2224/13021 , H01L2224/13022 , H01L2224/13099 , H01L2224/1319 , H01L2224/136 , H01L2224/16145 , H01L2224/81193 , H01L2224/81194 , H01L2224/81205 , H01L2224/81224 , H01L2224/81801 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/0001 , H01L2924/01006 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01059 , H01L2924/01079 , H01L2924/14 , H01L2924/351 , H01L2924/00014 , H01L2924/00
摘要： A chip structure and a stacked structure composed of the chip structures are provided. The chip structure has a substrate and at least one compliant contact. Furthermore, the chip structure may further have a redistribution layer for redistributing pads originally disposed around the substrate in a specific arrangement. The substrate has a first surface and a second surface. The compliant contact is embedded into the substrate and protrudes outside the first surface and the second surface of the substrate. The compliant contact has a compliant bump and a conductive layer encapsulating the compliant bump. The conductive layer can be connected with the redistribution layer. Two chip structures can be connected with each other through their compliant contacts or through their compliant contacts or redistribution layers.
摘要翻译：提供了由芯片结构构成的芯片结构和堆叠结构。芯片结构具有基底和至少一个顺应性接触。此外，芯片结构可以进一步具有再分配层，用于以特定布置重新分配初始设置在基板周围的焊盘。基板具有第一表面和第二表面。柔性接触件嵌入衬底中并突出到衬底的第一表面和第二表面之外。柔性接触件具有柔顺凸起和封装柔性凸起的导电层。导电层可以与再分布层连接。两个芯片结构可以通过它们的柔性触点或通过它们的柔性触点或再分布层彼此连接。

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