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1. 发明授权

US08304316B2 Semiconductor device and method of forming a semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08304316B2
公开(公告)日：2012-11-06
申请号：US11961410
申请日：2007-12-20
申请人： Florin Udrea , Gehan Anil Joseph Amaratunga , Tanya Trajkovic , Vasantha Pathirana
发明人： Florin Udrea , Gehan Anil Joseph Amaratunga , Tanya Trajkovic , Vasantha Pathirana
IPC分类号： H01L21/336
CPC分类号： H01L29/0657 , H01L21/8249 , H01L22/26 , H01L29/063 , H01L29/402 , H01L29/41725 , H01L29/41758 , H01L29/41775 , H01L29/7393 , H01L29/7816
摘要： In a power semiconductor device and a method of forming a power semiconductor device, a thin layer of semiconductor substrate is left below the drift region of a semiconductor device. A power semiconductor device has an active region that includes the drift region and has top and bottom surfaces formed in a layer provided on a semiconductor substrate. A portion of the semiconductor substrate below the active region is removed to leave a thin layer of semiconductor substrate below the drift region. Electrical terminals are provided directly or indirectly to the top surface of the active region to allow a voltage to be applied laterally across the drift region.
摘要翻译：在功率半导体器件和形成功率半导体器件的方法中，将半导体衬底的薄层留在半导体器件的漂移区域的下方。功率半导体器件具有包括漂移区的有源区，并且具有形成在设置在半导体衬底上的层中的顶表面和底表面。在有源区下面的半导体衬底的一部分被去除以在漂移区下方留下半导体衬底的薄层。电端子直接或间接提供到有源区的顶表面，以允许电压横向跨越漂移区域施加。

2. 发明授权

US08174069B2 Power semiconductor device and a method of forming a power semiconductor device 有权
标题翻译：功率半导体器件和形成功率半导体器件的方法
公开(公告)号：US08174069B2
公开(公告)日：2012-05-08
申请号：US12186231
申请日：2008-08-05
申请人： Florin Udrea , Vasantha Pathirana , Tanya Trajkovic , Nishad Udugampola
发明人： Florin Udrea , Vasantha Pathirana , Tanya Trajkovic , Nishad Udugampola
IPC分类号： H01L29/94
CPC分类号： H01L29/0847 , H01L29/0657 , H01L29/0839 , H01L29/0856 , H01L29/0878 , H01L29/4232 , H01L29/42372 , H01L29/7394 , H01L29/7824
摘要： A power semiconductor device has a top surface and an opposed bottom surface below a part of which is a thick portion of semiconductor substrate. At least a portion of a drift region of the device has either no or only a thin portion of semiconductor substrate positioned thereunder. The top surface has a high voltage terminal and a low voltage terminal connected thereto to allow a voltage to be applied laterally across the drift region. At least two MOS (metal-oxide-semiconductor) gates are provided on the top surface. The device has at least one relatively highly doped region at its top surface extending between and in contact with said first and second MOS gates. The device has improved protection against triggering of parasitic transistors or latch-up without the on-state voltage drop or switching speed being compromised.
摘要翻译：功率半导体器件具有顶表面和相对的底表面，其下面的一部分是半导体衬底的厚部分。装置的漂移区域的至少一部分具有没有或仅有半导体衬底的薄的部分位于其下方。顶表面具有高电压端子和与其连接的低电压端子，以允许跨越漂移区域横向施加电压。在顶表面上设置至少两个MOS（金属氧化物半导体）栅极。器件在其顶表面处具有至少一个相对高度掺杂的区域，其在所述第一和第二MOS栅极之间延伸并与之接触。该器件具有改进的防止寄生晶体管触发或闩锁的保护，而不会导致导通电压降或开关速度受损。

3. 发明申请

US20100032712A1 POWER SEMICONDUCTOR DEVICE AND A METHOD OF FORMING A POWER SEMICONDUCTOR DEVICE 有权
标题翻译：功率半导体器件和形成功率半导体器件的方法
公开(公告)号：US20100032712A1
公开(公告)日：2010-02-11
申请号：US12186231
申请日：2008-08-05
申请人： Florin UDREA , Vasantha PATHIRANA , Tanya TRAJKOVIC , Nishad UDUGAMPOLA
发明人： Florin UDREA , Vasantha PATHIRANA , Tanya TRAJKOVIC , Nishad UDUGAMPOLA
IPC分类号： H01L29/739 , H01L29/78 , H01L21/331 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/0657 , H01L29/0839 , H01L29/0856 , H01L29/0878 , H01L29/4232 , H01L29/42372 , H01L29/7394 , H01L29/7824
摘要： A power semiconductor device has a top surface and an opposed bottom surface below a part of which is a thick portion of semiconductor substrate. At least a portion of a drift region of the device has either no or only a thin portion of semiconductor substrate positioned thereunder. The top surface has a high voltage terminal and a low voltage terminal connected thereto to allow a voltage to be applied laterally across the drift region. At least two MOS (metal-oxide-semiconductor) gates are provided on the top surface. The device has at least one relatively highly doped region at its top surface extending between and in contact with said first and second MOS gates. The device has improved protection against triggering of parasitic transistors or latch-up without the on-state voltage drop or switching speed being compromised.
摘要翻译：功率半导体器件具有顶表面和相对的底表面，其下面的一部分是半导体衬底的厚部分。装置的漂移区域的至少一部分具有没有或仅有半导体衬底的薄的部分位于其下方。顶表面具有高电压端子和与其连接的低电压端子，以允许跨越漂移区域横向施加电压。在顶表面上设置至少两个MOS（金属氧化物半导体）栅极。器件在其顶表面处具有至少一个相对高度掺杂的区域，其在所述第一和第二MOS栅极之间延伸并与之接触。该器件具有改进的防止寄生晶体管触发或闩锁的保护，而不会导致导通电压降或开关速度受损。

4. 发明申请

US20090160015A1 SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及形成半导体器件的方法
公开(公告)号：US20090160015A1
公开(公告)日：2009-06-25
申请号：US11961410
申请日：2007-12-20
申请人： Florin UDREA , Gehan Anil Joseph Amaratunga , Tanya Trajkovic , Vasantha Pathirana
发明人： Florin UDREA , Gehan Anil Joseph Amaratunga , Tanya Trajkovic , Vasantha Pathirana
IPC分类号： H01L29/06 , H01L21/306
CPC分类号： H01L29/0657 , H01L21/8249 , H01L22/26 , H01L29/063 , H01L29/402 , H01L29/41725 , H01L29/41758 , H01L29/41775 , H01L29/7393 , H01L29/7816
摘要： In a power semiconductor device and a method of forming a power semiconductor device, a thin layer of semiconductor substrate is left below the drift region of a semiconductor device. A power semiconductor device has an active region that includes the drift region and has top and bottom surfaces formed in a layer provided on a semiconductor substrate. A portion of the semiconductor substrate below the active region is removed to leave a thin layer of semiconductor substrate below the drift region. Electrical terminals are provided directly or indirectly to the top surface of the active region to allow a voltage to be applied laterally across the drift region.
摘要翻译：在功率半导体器件和形成功率半导体器件的方法中，将半导体衬底的薄层留在半导体器件的漂移区域的下方。功率半导体器件具有包括漂移区的有源区，并且具有形成在设置在半导体衬底上的层中的顶表面和底表面。在有源区下面的半导体衬底的一部分被去除以在漂移区下方留下半导体衬底的薄层。电端子直接或间接提供到有源区的顶表面，以允许电压横向跨越漂移区域施加。

5. 发明授权

US08415712B2 Lateral insulated gate bipolar transistor (LIGBT) 失效
标题翻译：侧面绝缘栅双极晶体管（LIGBT）
公开(公告)号：US08415712B2
公开(公告)日：2013-04-09
申请号：US12648847
申请日：2009-12-29
申请人： Florin Udrea , Vasantha Pathirana , Tanya Trajkovic , Nishad Udugampola
发明人： Florin Udrea , Vasantha Pathirana , Tanya Trajkovic , Nishad Udugampola
IPC分类号： H01L29/739 , H01L21/331
CPC分类号： H01L29/7394 , H01L29/402
摘要： This invention generally relates to LIGBTs, ICs comprising an LIGBT and methods of forming an LIGBT, and more particularly to an LIGBT comprising a substrate region of first conductivity type and peak dopant concentration less than about 1×1017/cm3; a lateral drift region of a second, opposite conductivity type adjacent the substrate region and electrically coupled to said substrate region; a charge injection region of the first conductivity type to inject charge toward said lateral drift region; a gate to control flow of said charge in said lateral drift region; metal enriched adhesive below said substrate region; and an intermediate layer below said substrate region to substantially suppress charge injection into said substrate region from said metal enriched adhesive.
摘要翻译：本发明一般涉及LIGBT，包含LIGBT的IC和形成LIGBT的方法，更具体地涉及包含第一导电类型的衬底区域和小于约1×1017 / cm3的峰值掺杂剂浓度的LIGBT; 邻近所述衬底区域的第二相反导电类型的横向漂移区域，并电耦合到所述衬底区域; 第一导电类型的电荷注入区域，用于向所述横向漂移区域注入电荷; 用于控制所述横向漂移区域中的所述电荷的流动的门; 在所述衬底区域下面的富含金属的粘合剂; 以及在所述衬底区域下面的中间层，以基本上抑制从所述金属富集粘合剂向所述衬底区域注入电荷。

6. 发明申请

US20130069712A1 POWER SEMICONDUCTOR DEVICES AND FABRICATION METHODS 有权
标题翻译：功率半导体器件和制造方法
公开(公告)号：US20130069712A1
公开(公告)日：2013-03-21
申请号：US13233672
申请日：2011-09-15
申请人： Tanya Trajkovic , Florin Udrea , Vasantha Pathirana , Nishad Udugampola
发明人： Tanya Trajkovic , Florin Udrea , Vasantha Pathirana , Nishad Udugampola
IPC分类号： H01L29/78 , G05F3/02 , H01L21/336
CPC分类号： H01L29/0634 , H01L29/1033 , H01L29/1045 , H01L29/1095 , H01L29/42368 , H01L29/66325 , H01L29/66681 , H01L29/7393 , H01L29/7816 , H01L29/7824 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： We describe a RESURF semiconductor device having an n-drift region with a p-top layer and in which a MOS (Metal Oxide Semiconductor) channel of the device is formed within the p-top layer.
摘要翻译：我们描述了具有p顶层的n-漂移区的RESURF半导体器件，并且其中在该p顶层中形成该器件的MOS（金属氧化物半导体）沟道。

7. 发明授权

US08866252B2 Power semiconductor devices and fabrication methods 有权
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US08866252B2
公开(公告)日：2014-10-21
申请号：US13233672
申请日：2011-09-15
申请人： Tanya Trajkovic , Florin Udrea , Vasantha Pathirana , Nishad Udugampola
发明人： Tanya Trajkovic , Florin Udrea , Vasantha Pathirana , Nishad Udugampola
IPC分类号： H01L23/58 , H01L29/66 , H01L29/78 , H01L29/739 , H01L29/10 , H01L29/06 , H01L29/423
CPC分类号： H01L29/0634 , H01L29/1033 , H01L29/1045 , H01L29/1095 , H01L29/42368 , H01L29/66325 , H01L29/66681 , H01L29/7393 , H01L29/7816 , H01L29/7824 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： We describe a RESURF semiconductor device having an n-drift region with a p-top layer and in which a MOS (Metal Oxide Semiconductor) channel of the device is formed within the p-top layer.
摘要翻译：我们描述了具有p顶层的n-漂移区的RESURF半导体器件，并且其中在该p顶层中形成该器件的MOS（金属氧化物半导体）沟道。

8. 发明授权

US08482031B2 Lateral insulated gate bipolar transistors (LIGBTS) 失效
标题翻译：横向绝缘栅双极晶体管（LIGBTS）
公开(公告)号：US08482031B2
公开(公告)日：2013-07-09
申请号：US12648818
申请日：2009-12-29
申请人： Florin Udrea , Vasantha Pathirana , Tanya Trajkovic , Nishad Udugampola
发明人： Florin Udrea , Vasantha Pathirana , Tanya Trajkovic , Nishad Udugampola
IPC分类号： H01L29/739 , H01L21/761 , H01L21/331
CPC分类号： H01L29/7394 , H01L29/66325 , H01L29/7393
摘要： This invention generally relates to lateral insulated gate bipolar transistors (LIGBTs), for example in integrated circuits, methods of increasing switching speed of an LIGBT, a method of suppressing parasitic thyristor latch-up in a bulk silicon LIGBT, and methods of fabricating an LIGBT. In particular, a method of suppressing parasitic thyristor latch-up in a bulk silicon LIGBT comprises selecting a current gain αv for a vertical transistor of a parasitic thyristor of the LIGBT such that in at least one predetermined mode of operation of the LIGBT αv
摘要翻译：本发明一般涉及横向绝缘栅双极晶体管（LIGBT），例如在集成电路中，提高LIGBT的开关速度的方法，抑制体硅LIGBT中的寄生晶闸管闩锁的方法以及制造LIGBT的方法。特别地，抑制体硅LIGBT中的寄生晶闸管闩锁的方法包括为LIGBT的寄生晶闸管的垂直晶体管选择电流增益α，使得在LIGBT的至少一个预定操作模式中，alphav <1 其中alphap是具有由半导体表面和富含金属的环氧树脂裸片附着之间的肖特基接触形成的基极 - 发射极的寄生双极晶体管的电流增益。

9. 发明申请

US20110156096A1 Lateral Insulated Gate Bipolar Transistor (LIGBT) 失效
标题翻译：侧面绝缘栅双极晶体管（LIGBT）
公开(公告)号：US20110156096A1
公开(公告)日：2011-06-30
申请号：US12648847
申请日：2009-12-29
申请人： Florin Udrea , Vasantha Pathirana , Tanya Trajkovic , Nishad Udugampola
发明人： Florin Udrea , Vasantha Pathirana , Tanya Trajkovic , Nishad Udugampola
IPC分类号： H01L29/739 , H01L21/331
CPC分类号： H01L29/7394 , H01L29/402
摘要： This invention generally relates to LIGBTs, ICs comprising an LIGBT and methods of forming an LIGBT, and more particularly to an LIGBT comprising a substrate region of first conductivity type and peak dopant concentration less than about 1×1017/cm3; a lateral drift region of a second, opposite conductivity type adjacent the substrate region and electrically coupled to said substrate region; a charge injection region of the first conductivity type to inject charge toward said lateral drift region; a gate to control flow of said charge in said lateral drift region; metal enriched adhesive below said substrate region; and an intermediate layer below said substrate region to substantially suppress charge injection into said substrate region from said metal enriched adhesive.
摘要翻译：本发明一般涉及LIGBT，包含LIGBT的IC和形成LIGBT的方法，更具体地涉及包含第一导电类型的衬底区域和小于约1×1017 / cm3的峰值掺杂剂浓度的LIGBT; 邻近所述衬底区域的第二相反导电类型的横向漂移区域，并电耦合到所述衬底区域; 第一导电类型的电荷注入区域，用于向所述横向漂移区域注入电荷; 用于控制所述横向漂移区域中的所述电荷的流动的门; 在所述衬底区域下面的富含金属的粘合剂; 以及在所述衬底区域下面的中间层，以基本上抑制从所述金属富集粘合剂向所述衬底区域注入电荷。

10. 发明申请

US20110057230A1 Lateral Insulated Gate Bipolar Transistors (LIGBTS) 失效
标题翻译：侧面绝缘栅双极晶体管（LIGBTS）
公开(公告)号：US20110057230A1
公开(公告)日：2011-03-10
申请号：US12648818
申请日：2009-12-29
申请人： Florin Udrea , Vasantha Pathirana , Tanya Trajkovic , Nishad Udugampola
发明人： Florin Udrea , Vasantha Pathirana , Tanya Trajkovic , Nishad Udugampola
IPC分类号： H01L29/739 , H01L21/761 , H01L21/331
CPC分类号： H01L29/7394 , H01L29/66325 , H01L29/7393
摘要： This invention generally relates to lateral insulated gate bipolar transistors (LIGBTs), for example in integrated circuits, methods of increasing switching speed of an LIGBT, a method of suppressing parasitic thyristor latch-up in a bulk silicon LIGBT, and methods of fabricating an LIGBT. In particular, a method of suppressing parasitic thyristor latch-up in a bulk silicon LIGBT comprises selecting a current gain αv for a vertical transistor of a parasitic thyristor of the LIGBT such that in at least one predetermined mode of operation of the LIGBT αv
摘要翻译：本发明一般涉及横向绝缘栅双极晶体管（LIGBT），例如在集成电路中，提高LIGBT的开关速度的方法，抑制体硅LIGBT中的寄生晶闸管闩锁的方法以及制造LIGBT的方法。特别地，抑制体硅LIGBT中的寄生晶闸管闩锁的方法包括为LIGBT的寄生晶闸管的垂直晶体管选择电流增益αv，使得在LIGBT的至少一个预定操作模式中，αv<1 -αp，其中αp是具有由半导体表面和富含金属的环氧树脂芯片之间的肖特基接触形成的基极 - 发射极结的寄生双极晶体管的电流增益。

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