专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08278199B2 Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US08278199B2
公开(公告)日：2012-10-02
申请号：US13242000
申请日：2011-09-23
申请人： Shigenari Okada , Takuya Futase , Yutaka Inaba
发明人： Shigenari Okada , Takuya Futase , Yutaka Inaba
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/67184 , H01L21/67207 , H01L21/823835 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L2224/11
摘要： Reliability of a semiconductor element and its product yield are improved by reducing variations in the electrical characteristic of a metal silicide layer. After forming a nickel-platinum alloy film over a semiconductor substrate, by carrying out a first thermal treatment at a thermal treatment temperature of 210 to 310° C. using a heater heating device, the technique causes the nickel-platinum alloy film and silicon to react with each other to form a platinum-added nickel silicide layer in a (PtNi)2Si phase. After removing unreacted nickel-platinum alloy film, the technique carries out a second thermal treatment having the thermal treatment temperature higher than that of the first thermal treatment to form the platinum-added nickel silicide layer in a PtNiSi phase. The temperature rise rate of each thermal treatment is set to 10° C./s or more.
摘要翻译：通过减少金属硅化物层的电特性的变化来改善半导体元件的可靠性及其产品产率。在半导体基板上形成镍 - 铂合金膜之后，通过使用加热器加热装置在210〜310℃的热处理温度下进行第一次热处理，由此使镍 - 铂合金膜和硅彼此反应以在（PtNi）2 Si相中形成添加铂的硅化镍层。在除去未反应的镍 - 铂合金膜之后，该技术进行热处理温度高于第一热处理的第二热处理，以在PtNiSi相中形成添加铂的硅化镍层。各热处理的升温速度设定为10℃/ s以上。

2. 发明授权

US08268682B2 Method for manufacturing a semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US08268682B2
公开(公告)日：2012-09-18
申请号：US13049889
申请日：2011-03-16
申请人： Takuya Futase , Shuhei Murata , Takeshi Hayashi
发明人： Takuya Futase , Shuhei Murata , Takeshi Hayashi
IPC分类号： H01L21/336
CPC分类号： H01L21/67167 , H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L29/7843
摘要： When a natural oxide film is left at the interface between a metal silicide layer and a silicon nitride film, in various heating steps (steps involving heating of a semiconductor substrate, such as various insulation film and conductive film deposition steps) after deposition of the silicon nitride film, the metal silicide layer partially abnormally grows due to oxygen of the natural oxide film occurring on the metal silicide layer surface. A substantially non-bias (including low bias) plasma treatment is performed in a gas atmosphere containing an inert gas as a main component on the top surface of a metal silicide film of nickel silicide or the like over source/drain of a field-effect transistor forming an integrated circuit. Then, a silicon nitride film serving as an etching stop film of a contact process is deposited. As a result, without causing undesirable cutting of the metal silicide film, the natural oxide film over the top surface of the metal silicide film can be removed.
摘要翻译：在金属硅化物层和氮化硅膜之间的界面处留有自然氧化膜时，在各种加热步骤（包括加热半导体衬底，诸如各种绝缘膜和导电膜沉积步骤的步骤）之后，硅沉积由于在金属硅化物层表面上发生的自然氧化膜的氧，金属硅化物层部分地异常生长。基于非偏置（包括低偏压）等离子体处理在含有惰性气体作为主要成分的气体气氛中，在场效应源极/漏极上的硅化镍等的金属硅化物膜的顶表面上进行晶体管形成集成电路。然后，沉积作为接触处理的蚀刻停止膜的氮化硅膜。结果，不会导致金属硅化物膜的不期望的切割，可以去除金属硅化物膜的顶表面上方的自然氧化膜。

3. 发明申请

US20110248355A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110248355A1
公开(公告)日：2011-10-13
申请号：US13085478
申请日：2011-04-13
申请人： Takuya FUTASE
发明人： Takuya FUTASE
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L21/823425 , H01L21/28052 , H01L21/28518 , H01L21/823468 , H01L21/823814 , H01L21/823864 , H01L27/0629 , H01L29/665
摘要： An improvement is achieved in the performance of a semiconductor device in which a metal silicide layer is formed by a salicide process. In a main surface of a semiconductor substrate, a plurality of MISFETs are formed, each having a gate electrode, and source/drain regions over each of which the metal silicide layer is formed. The metal silicide layer is formed of a silicide of nickel and a first metal element including at least one selected from the group consisting of Pt, Pd, V, Er, and Yb. A grain size in the metal silicide layer is smaller than the width in a gate length direction of the source/drain region included in the source/drain regions of the plurality of MISFETs formed in the main surface of the semiconductor substrate, and disposed between the gate electrodes adjacent in closest proximity to each other in the gate length direction.
摘要翻译：在其中通过自对准硅化物工艺形成金属硅化物层的半导体器件的性能方面获得了改进。在半导体衬底的主表面中，形成多个MISFET，每个MISFET具有栅电极，并且在其上形成有金属硅化物层的源/漏区。金属硅化物层由镍的硅化物和包含选自Pt，Pd，V，Er和Yb中的至少一种的第一金属元素形成。金属硅化物层中的晶粒尺寸小于形成在半导体衬底的主表面中的多个MISFET的源极/漏极区域中包括的源极/漏极区域的栅极长度方向上的宽度，并且设置在栅电极在栅极长度方向上彼此最接近地相邻。

4. 发明授权

US08034717B2 Mass production method of semiconductor integrated circuit device and manufacturing method of electronic device 有权
公开(公告)号：US08034717B2
公开(公告)日：2011-10-11
申请号：US12207530
申请日：2008-09-10
申请人： Takuya Futase , Tomonori Saeki , Mieko Kashi
发明人： Takuya Futase , Tomonori Saeki , Mieko Kashi
IPC分类号： H01L21/44
CPC分类号： C23F1/30 , H01L21/32134 , H01L27/10814 , H01L28/55 , H01L28/60 , Y10S134/902
摘要： In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film).

5. 发明申请

US20110237061A1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20110237061A1
公开(公告)日：2011-09-29
申请号：US13046761
申请日：2011-03-13
申请人： Tadashi Yamaguchi , Takuya Futase
发明人： Tadashi Yamaguchi , Takuya Futase
IPC分类号： H01L21/28
CPC分类号： H01L21/28052 , H01L21/28518 , H01L21/67207 , H01L21/67748 , H01L21/68735 , H01L21/68764 , H01L21/823814 , H01L21/823835 , H01L29/665
摘要： The present invention improves the performance of a semiconductor device wherein a metal silicide layer is formed through a salicide process. A metal silicide layer is formed over the surfaces of first and second gate electrodes, n+-type semiconductor regions, and p+-type semiconductor regions through a salicide process of a partial reaction type without the use of a salicide process of a whole reaction type. In a heat treatment for forming the metal silicide layer, by heat-treating a semiconductor wafer not with an annealing apparatus using lamps or lasers but with a thermal conductive annealing apparatus using carbon heaters, a thin metal silicide layer is formed with a small thermal budget and a high degree of accuracy and microcrystals of NiSi are formed in the metal silicide layer through a first heat treatment.
摘要翻译：本发明改进了通过自对准硅化物工艺形成金属硅化物层的半导体器件的性能。通过部分反应型的自对准硅化物工艺，在不使用整个反应类型的自对准硅化物工艺的情况下，在第一和第二栅电极，n +型半导体区域和p +型半导体区域的表面上形成金属硅化物层。在用于形成金属硅化物层的热处理中，通过不使用灯或激光器的退火设备对半导体晶片进行热处理，但是使用具有碳加热器的导热退火装置，以小的热预算形成薄金属硅化物层并且通过第一热处理在金属硅化物层中形成高精度的NiSi微晶。

6. 发明申请

US20110165743A1 METHOD FOR MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US20110165743A1
公开(公告)日：2011-07-07
申请号：US13049889
申请日：2011-03-16
申请人： TAKUYA FUTASE , Shuhei Murata , Takeshi Hayashi
发明人： TAKUYA FUTASE , Shuhei Murata , Takeshi Hayashi
IPC分类号： H01L21/336
CPC分类号： H01L21/67167 , H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L29/7843
摘要： When a natural oxide film is left at the interface between a metal silicide layer and a silicon nitride film, in various heating steps (steps involving heating of a semiconductor substrate, such as various insulation film and conductive film deposition steps) after deposition of the silicon nitride film, the metal silicide layer partially abnormally grows due to oxygen of the natural oxide film occurring on the metal silicide layer surface. A substantially non-bias (including low bias) plasma treatment is performed in a gas atmosphere containing an inert gas as a main component on the top surface of a metal silicide film of nickel silicide or the like over source/drain of a field-effect transistor forming an integrated circuit. Then, a silicon nitride film serving as an etching stop film of a contact process is deposited. As a result, without causing undesirable cutting of the metal silicide film, the natural oxide film over the top surface of the metal silicide film can be removed.
摘要翻译：在金属硅化物层和氮化硅膜之间的界面处留有自然氧化物膜时，在各种加热步骤（包括加热半导体衬底，诸如各种绝缘膜和导电膜沉积步骤的步骤）之后，沉积硅由于在金属硅化物层表面上发生的自然氧化膜的氧，金属硅化物层部分地异常生长。基于非偏置（包括低偏压）等离子体处理在含有惰性气体作为主要成分的气体气氛中，在场效应源极/漏极上的硅化镍等的金属硅化物膜的顶表面上进行晶体管形成集成电路。然后，沉积作为接触处理的蚀刻停止膜的氮化硅膜。结果，不会导致金属硅化物膜的不期望的切割，可以去除金属硅化物膜的顶表面上方的自然氧化膜。

7. 发明授权

US07964500B2 Method of manufacturing semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US07964500B2
公开(公告)日：2011-06-21
申请号：US12714491
申请日：2010-02-27
申请人： Takuya Futase
发明人： Takuya Futase
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/02063 , H01L21/28556 , H01L21/67028 , H01L21/67207 , H01L21/76846 , H01L21/76855 , H01L21/76873 , H01L21/76876 , H01L21/76877 , H01L21/76895 , H01L27/11 , H01L27/1104
摘要： To solve a problem that it becomes difficult to lower contact resistance between nickel-based metal silicide and metal for contact as the result of the miniaturization of the hole. One invention of the present application is a method of manufacturing a semiconductor integrated circuit device having a MISFET subjected to silicidation of a source/drain region and the like by nickel-based metal silicide, the method performing a heat treatment for the upper surface of a silicide film in a non-plasma reducing vapor phase atmosphere containing a gas having a nitrogen-hydrogen bond as one of main gas components, before forming a barrier metal at a contact hole provided at a pre-metal insulating film.
摘要翻译：为了解决由于孔的小型化而导致的镍基金属硅化物与金属接触难以降低接触电阻的问题。本申请的一个发明是一种制造半导体集成电路器件的方法，该半导体集成电路器件具有通过镍基金属硅化物对源极/漏极区等进行硅化处理的MISFET，该方法对于上述表面进行热处理在设置在预金属绝缘膜上的接触孔处形成阻挡金属之前，在含有具有氮 - 氢键的气体作为主要气体成分之一的非等离子体还原气相气氛中的硅化物膜。

8. 发明授权

US07923319B2 Method for manufacturing a semiconductor integrated circuit device circuit device 有权
标题翻译：半导体集成电路器件电路器件的制造方法
公开(公告)号：US07923319B2
公开(公告)日：2011-04-12
申请号：US12622524
申请日：2009-11-20
申请人： Takuya Futase , Shuhei Murata , Takeshi Hayashi
发明人： Takuya Futase , Shuhei Murata , Takeshi Hayashi
IPC分类号： H01L21/336
CPC分类号： H01L21/67167 , H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L29/7843
摘要： When a natural oxide film is left at the interface between a metal silicide layer and a silicon nitride film, in various heating steps (steps involving heating of a semiconductor substrate, such as various insulation film and conductive film deposition steps) after deposition of the silicon nitride film, the metal silicide layer partially abnormally grows due to oxygen of the natural oxide film occurring on the metal silicide layer surface. A substantially non-bias (including low bias) plasma treatment is performed in a gas atmosphere containing an inert gas as a main component on the top surface of a metal silicide film of nickel silicide or the like over source/drain of a field-effect transistor forming an integrated circuit. Then, a silicon nitride film serving as an etching stop film of a contact process is deposited. As a result, without causing undesirable cutting of the metal silicide film, the natural oxide film over the top surface of the metal silicide film can be removed.
摘要翻译：在金属硅化物层和氮化硅膜之间的界面处留有自然氧化物膜时，在各种加热步骤（包括加热半导体衬底，诸如各种绝缘膜和导电膜沉积步骤的步骤）之后，沉积硅由于在金属硅化物层表面上发生的自然氧化膜的氧，金属硅化物层部分地异常生长。基于非偏置（包括低偏压）等离子体处理在含有惰性气体作为主要成分的气体气氛中，在场效应源极/漏极上的硅化镍等的金属硅化物膜的顶表面上进行晶体管形成集成电路。然后，沉积作为接触处理的蚀刻停止膜的氮化硅膜。结果，不会导致金属硅化物膜的不期望的切割，可以去除金属硅化物膜的顶表面上方的自然氧化膜。

9. 发明申请

US20090011566A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20090011566A1
公开(公告)日：2009-01-08
申请号：US12167445
申请日：2008-07-03
申请人： Shigenari Okada , Takuya Futase
发明人： Shigenari Okada , Takuya Futase
IPC分类号： H01L21/44 , H01L21/336
CPC分类号： H01L21/76224 , H01L21/0206 , H01L21/28518 , H01L21/324 , H01L21/67184 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： After gate insulating films, gate electrodes, and n+ type semiconductor regions and p+ type semiconductor regions for source/drain are formed, a metal film and a barrier film are formed on a semiconductor substrate. And a first heat treatment is performed so as to make the metal film react with the gate electrodes, the n+ type semiconductor region, and the p+ type semiconductor region, thereby forming a metal silicide layer formed of a monosilicide of a metal element forming the metal film. After that, the barrier film and the unreacted metal film are removed, and then a second heat treatment is performed to stabilize the metal silicide layer. The heat treatment temperature is made lower than a temperature at which a lattice size of a disilicide of the metal element and that of the semiconductor substrate become same.
摘要翻译：在栅极绝缘膜之后，形成用于源极/漏极的栅电极和n +型半导体区域和p +型半导体区域，在半导体衬底上形成金属膜和阻挡膜。进行第一热处理，以使金属膜与栅电极，n +型半导体区域和p +型半导体区域反应，由此形成由形成金属的金属元素的一硅化物形成的金属硅化物层电影。之后，除去阻挡膜和未反应的金属膜，然后进行第二次热处理以稳定金属硅化物层。使热处理温度低于金属元素的二硅化物的晶格尺寸和半导体衬底的晶体尺寸相同的温度。

10. 发明授权

US08110457B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08110457B2
公开(公告)日：2012-02-07
申请号：US12563144
申请日：2009-09-20
申请人： Takuya Futase
发明人： Takuya Futase
IPC分类号： H01L21/336
CPC分类号： H01L21/68735 , H01L21/28052 , H01L21/28518 , H01L21/67109 , H01L21/67184 , H01L21/6719 , H01L29/665 , H01L29/6656
摘要： To provide a semiconductor device with improved reliability which includes a metal silicide layer formed by a salicide process. After forming gate electrodes, an n+-type semiconductor region, and a p+-type semiconductor region for a source or drain, a Ni1−xPtx alloy film is formed over a semiconductor substrate. The alloy film reacts with the gate electrodes, the n+-type semiconductor region, and the p+-type semiconductor region by a first heat treatment to form a metal silicide layer in a (Ni1−yPty)2Si phase. At this time, the first heat treatment is performed at a heat treatment temperature where a diffusion coefficient of Ni is larger than that of Pt. Further, the first heat treatment is performed such that a reacted part of the alloy film remains at the metal silicide layer. This results in y>x. Then, after removing the unreacted part of the alloy film, the metal silicide layer is further subjected to a second heat treatment to form a metal silicide layer in a Ni1−yPtySi phase.
摘要翻译：提供具有改善的可靠性的半导体器件，其包括通过自对准硅化物工艺形成的金属硅化物层。在形成栅电极，n +型半导体区域和用于源极或漏极的p +型半导体区域之后，在半导体衬底上形成Ni1-xPtx合金膜。合金膜通过第一次热处理与栅电极，n +型半导体区域和p +型半导体区域反应，以形成（Ni1-yPty）2Si相中的金属硅化物层。此时，第一热处理在Ni的扩散系数大于Pt的扩散系数的热处理温度下进行。此外，进行第一热处理，使得合金膜的反应部分残留在金属硅化物层。这导致y> x。然后，在除去合成膜的未反应部分之后，进一步对金属硅化物层进行第二次热处理，以在Ni1-yPtySi相中形成金属硅化物层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式