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1. 发明申请

US20050187750A1 Data processing device designing method, data processing device designing apparatus, program and computer readable information recording medium 失效
标题翻译：数据处理装置设计方法，数据处理装置设计装置，程序和计算机可读信息记录介质
公开(公告)号：US20050187750A1
公开(公告)日：2005-08-25
申请号：US11018964
申请日：2004-12-22
申请人： Masaoki Satoh , Takeshi Toyoyama , Satoshi Aoki
发明人： Masaoki Satoh , Takeshi Toyoyama , Satoshi Aoki
IPC分类号： G06F11/28 , G06F11/34 , G06F17/50
CPC分类号： G06F17/5045 , G06F17/5022
摘要： A method includes steps of calculating, for each predetermined operation included in a program, an execution time required when the operation is executed by a predetermined processor, or calculating, for each predetermined operation included in the program, a circuit size required when the operation is realized in a form of hardware according to a predetermined technology; and calculating, for the entirety of the predetermined program or operations corresponding to a part the entirety of the predetermined program, a total execution time required when the entirety of the predetermined program is executed by the predetermined processor, as a result of applying in sequence the required execution time, or calculating, for the entirety of the predetermined program or operations corresponding to a part the entirety of the predetermined program, a total circuit size required when the entirety of the predetermined program or programs corresponding to a part of the entirety of the predetermined program, as a result of applying in sequence the required circuit size.
摘要翻译：一种方法包括以下步骤：对于包括在程序中的每个预定操作，计算当由预定处理器执行操作所需的执行时间，或者对于包括在程序中的每个预定操作，计算操作所需的电路大小根据预定技术以硬件形式实现; 并且对于与预定程序的整体的一部分相对应的预定程序或操作的整体，计算由预定处理器执行预定程序的整体所需的总执行时间，作为依次应用的结果所需的执行时间或计算对应于预定程序的整体的一部分的预定程序或操作的整体，当整个预定程序或程序的整体的一部分相对应时，所需的总电路大小作为依次应用所需电路尺寸的结果的预定程序。

2. 发明授权

US06895473B2 Data control device and an ATM control device 有权
标题翻译：数据控制装置和ATM控制装置
公开(公告)号：US06895473B2
公开(公告)日：2005-05-17
申请号：US10298973
申请日：2002-11-12
申请人： Masao Nakano , Takeshi Toyoyama , Yasuhiro Ooba
发明人： Masao Nakano , Takeshi Toyoyama , Yasuhiro Ooba
IPC分类号： G06F15/167 , G06F15/173 , H04L12/70 , H04L12/937 , H04Q11/04 , G06F12/00
CPC分类号： H04Q11/0478 , H04L2012/5625
摘要： A data control device capable of high-quality, high-efficiency control for speeding up data processing, thus permitting improvement of the throughput of a system. Attribute analyzing unit analyzes an attribute of data, and a main memory stores setting information of the data in a region corresponding to the attribute. A highway cache memory stores the data, and also receives and transmits the data on a highway. A processor performs an operation on the data in accordance with the setting information. A data cache memory is interposed between the processor and the main memory and stores the setting information.
摘要翻译：一种能够进行高质量，高效率控制的数据控制装置，用于加速数据处理，从而可以提高系统的吞吐量。属性分析单元分析数据的属性，并且主存储器将数据的设置信息存储在与属性相对应的区域中。公路缓存存储器存储数据，并且还在高速公路上接收和发送数据。处理器根据设置信息对数据进行操作。在处理器和主存储器之间插入数据高速缓冲存储器并存储设置信息。

3. 发明授权

US07447617B2 Data processing device designing method, data processing device designing apparatus, program and computer readable information recording medium 失效
标题翻译：数据处理装置设计方法，数据处理装置设计装置，程序和计算机可读信息记录介质
公开(公告)号：US07447617B2
公开(公告)日：2008-11-04
申请号：US11018964
申请日：2004-12-22
申请人： Masaoki Satoh , Takeshi Toyoyama , Satoshi Aoki
发明人： Masaoki Satoh , Takeshi Toyoyama , Satoshi Aoki
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5022
摘要： A method includes steps of calculating, for each predetermined operation included in a program, an execution time required when the operation is executed by a predetermined processor, or calculating, for each predetermined operation included in the program, a circuit size required when the operation is realized in a form of hardware according to a predetermined technology; and calculating, for the entirety of the predetermined program or operations corresponding to a part the entirety of the predetermined program, a total execution time required when the entirety of the predetermined program is executed by the predetermined processor, as a result of applying in sequence the required execution time, or calculating, for the entirety of the predetermined program or operations corresponding to a part the entirety of the predetermined program, a total circuit size required when the entirety of the predetermined program or programs corresponding to a part of the entirety of the predetermined program, as a result of applying in sequence the required circuit size.
摘要翻译：一种方法包括以下步骤：对于包括在程序中的每个预定操作，计算当由预定处理器执行操作所需的执行时间，或者对于包括在程序中的每个预定操作，计算操作所需的电路大小根据预定技术以硬件形式实现; 并且对于与预定程序的整体的一部分相对应的预定程序或操作的整体，计算由预定处理器执行预定程序的整体所需的总执行时间，作为依次应用的结果所需的执行时间或计算对应于预定程序的整体的一部分的预定程序或操作的整体，当整个预定程序或程序的整体的一部分相对应时，所需的总电路大小作为依次应用所需电路尺寸的结果的预定程序。

4. 发明授权

US06826673B2 Communications protocol processing by real time processor off-loading operations to queue for processing by non-real time processor 失效
标题翻译：通信协议处理通过实时处理器卸载操作进行队列处理，由非实时处理器
公开(公告)号：US06826673B2
公开(公告)日：2004-11-30
申请号：US09775160
申请日：2001-02-01
申请人： Takeshi Toyoyama , Masao Nakano , Yasuhiro Ooba
发明人： Takeshi Toyoyama , Masao Nakano , Yasuhiro Ooba
IPC分类号： G06F15167
CPC分类号： H04Q11/0478 , H04L2012/5651 , H04L2012/5671
摘要： A communication protocol processing unit by a multiprocessor is disclosed, and includes a first processor for performing a process demanding a real time property on a stream of communication data; and a second processor for performing a process not demanding the real time property, wherein the first processor transfers using parameters paired with the communication data to be processed to the second processor, and the second processor is structured so as to refer to the transferred communication data and parameters to process.
摘要翻译：公开了一种通过多处理器的通信协议处理单元，并且包括：第一处理器，用于执行要求通信数据流上的实时属性的处理; 以及用于执行不要求实时性的处理的第二处理器，其中所述第一处理器使用与要处理的所述通信数据配对的参数来传送到所述第二处理器，并且所述第二处理器被构造为参考所传送的通信数据和参数进行处理。

5. 发明授权

US07545831B2 Transmission device for processing and transmitting signals of a plurality of channels 失效
标题翻译：用于处理和发送多个信道的信号的传输设备
公开(公告)号：US07545831B2
公开(公告)日：2009-06-09
申请号：US10098999
申请日：2002-03-14
申请人： Takeshi Toyoyama , Masao Nakano , Shosaku Yamasaki , Shigehisa Sakahara
发明人： Takeshi Toyoyama , Masao Nakano , Shosaku Yamasaki , Shigehisa Sakahara
IPC分类号： H04J3/00
CPC分类号： H04J3/08 , H04J3/14 , H04J2203/0042 , H04J2203/006 , Y10S370/907
摘要： A transmission device performing prescribed processing on signals of a plurality of channels and transmitting the signals of the plurality of channels. The device includes a first storage unit for storing, in different memory cells for each channel, first control data in which one or more types of control data elements for each channel are configured as at least one word data; a first data structure conversion unit for selecting control data elements of the same type from the first control data of the plurality of channels stored in the first storage unit, and converting the structure of the first control data such that the control data elements of the same type are configured as one word data; and a data generation unit for processing, in word units, the first control data after conversion by the first data structure conversion unit, and generating second control data necessary for the prescribed processing.
摘要翻译：发送装置对多个信道的信号进行规定处理，并发送多个信道的信号。该设备包括：第一存储单元，用于在每个信道的不同存储器单元中存储用于每个通道的一个或多个类型的控制数据元素被配置为至少一个字数据的第一控制数据; 第一数据结构转换单元，用于从存储在第一存储单元中的多个通道的第一控制数据中选择相同类型的控制数据元素，并且转换第一控制数据的结构，使得其的控制数据元素类型被配置为一个字数据; 以及数据生成单元，用于以单位单位处理由第一数据结构转换单元转换之后的第一控制数据，并且生成规定处理所需的第二控制数据。

6. 发明授权

US6157658A Pointer processing apparatus, POH terminating process apparatus, method of POH terminating process and pointer/POH terminating process apparatus in SDH transmission system 失效
标题翻译：指针处理装置，POH终端处理装置，POH终止处理方法和SDH传输系统中的指针/ POH终止处理装置
公开(公告)号：US6157658A
公开(公告)日：2000-12-05
申请号：US852841
申请日：1997-05-07
申请人： Takeshi Toyoyama , Hiroshi Yoshida , Hideo Emoto , Hisayoshi Kuraya , Masanobu Edasawa
发明人： Takeshi Toyoyama , Hiroshi Yoshida , Hideo Emoto , Hisayoshi Kuraya , Masanobu Edasawa
IPC分类号： H04J3/00 , H04J3/04 , H04J3/06 , H04L12/28
CPC分类号： H04J3/0623 , Y10S370/907
摘要： A pointer processing apparatus in an SDH transmission system used to serially conducting a pointer process on inputted multiplex data has an address generating unit for allocating an address to each channel of the multiplex data, a RAM for holding an information group obtained by a pointer extracting process and a pointer process, and RAM controlling unit for controlling a sequence of an operation to write-in/read-out the RAM to serially conduct the pointer process on the received multiplex data, thereby largely decreasing the circuit scale, the power consumption, the number of distributions and the like. A POH terminating operation process is conducted in a POH terminating operation process unit, and an obtained result of the POH terminating operation is stored in a storage area for a corresponding channel of a storage unit, whereby the POH terminating operation process can be conducted without separating a multiplex signal into channels. By conducting the POH terminating operation process on the multiplex signal without separating the multiplex signal into channels, a scale and a power consumption of an apparatus can be largely decreased.
摘要翻译：用于在输入的多路复用数据上串行地进行指针处理的SDH传输系统中的指针处理装置具有：地址生成单元，用于向多路复用数据的每个通道分配地址; RAM，用于保存通过指针提取处理获得的信息组指针处理和RAM控制单元，用于控制写入/读出RAM的操作的顺序，以对所接收的多路复用数据串行地进行指针处理，从而大大降低电路规模，功耗，分布数等。在POH终止操作处理单元中执行POH终止操作处理，并且将获得的POH终止操作的结果存储在存储单元的相应通道的存储区域中，从而可以在不分离的情况下进行POH终止操作处理将多路复用信号转换成通道。通过对多路复用信号进行POH终止操作处理而不将多路复用信号分离成通道，可以大大降低装置的规模和功耗。

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