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1. 发明专利

JP2005258253A Snare drum 有权
标题翻译：小鼓
公开(公告)号：JP2005258253A
公开(公告)日：2005-09-22
申请号：JP2004072219
申请日：2004-03-15
申请人： Takeshi Nojima , 豪野嶋
发明人： NOJIMA TAKESHI
IPC分类号： G10D13/00 , G10D13/02
摘要： PROBLEM TO BE SOLVED: To realize a snare drum capable of generating attack sound which is rich in forceful feeling over a whole sound region ranging from a low-pitched sound region to a high-pitched sound region and also is rich in clear feeling. SOLUTION: A strainer 10 for making the tensity of a snare tight by lacing and stopping one side of stopping strings which are connected respectively to both ends of the snare is supported by a supporting member 14 having the shape of a plate whose width is narrow which is fixed to two adjacent lugs 20a, 20b of a plurality of lugs connecting a top rim 52 and a bottom rim 53. A lacing and stopping tool 30 which laces and stops another lacing and stopping string is supported by a supporting member 34 having the shape of a plate whose width is narrow which is fixed to two adjacent rugs 20c, 20d. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：实现能够产生从低音区域到高音区域的整个声音区域中具有强烈感觉的攻击声的小鼓，并且还具有丰富的清晰度感觉。解决方案：用于通过系紧和阻止分别与圈套两端连接的止动绳的一侧来制作圈套的过滤器10由具有板形形状的支撑构件14支撑，该支撑构件的宽度是狭窄的，其被固定到连接顶部边缘52和底部边缘53的多个凸耳的两个相邻的凸耳20a，20b。鞋带和止动工具30，其装饰并阻止另一个鞋带和止动弦由支撑构件34支撑具有固定在两个相邻的地毯20c，20d上的宽度窄的板的形状。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2011053239A Drum 有权
标题翻译：鼓
公开(公告)号：JP2011053239A
公开(公告)日：2011-03-17
申请号：JP2009199213
申请日：2009-08-31
申请人： Takeshi Nojima , 豪野嶋
发明人： NOJIMA TAKESHI
IPC分类号： G10D13/00 , G10D13/02
摘要： PROBLEM TO BE SOLVED: To provide a drum capable of giving a well balanced and long echoing beat sound with a constitution of small number of constituent parts. SOLUTION: The drum includes a lug 20 connecting a top rim for keeping tight tension of a top head with a bottom rim for keeping tight tension of a bottom head, wherein the lug 20 includes: a screw hole for screwing thereinto a cylindrically formed hexagon bolt 11 having an air hole 12, which penetrates a shell 51 having no vent hole for releasing air and which is inserted through a support 60 for supporting the lug 20; and a hole 21 for releasing air in the shell 51 to the outside, which communicates with the screw hole. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够以少量组成部件的构造给出良好平衡和长回波的声音的鼓。解决方案：滚筒包括连接顶部边缘的凸耳20，用于保持顶部头部的紧固张力与底部边缘，用于保持底部头部的紧张张力，其中凸耳20包括：螺纹孔，用于将圆柱形形成有六角螺栓11，其具有空气孔12，其穿透没有用于释放空气的通气孔的壳体51，并且插入通过用于支撑凸耳20的支撑件60; 以及用于将壳体51中的空气释放到与螺钉孔连通的外部的孔21。版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2006065156A Strainer of snare drum 审中-公开
标题翻译： SN。。。
公开(公告)号：JP2006065156A
公开(公告)日：2006-03-09
申请号：JP2004249664
申请日：2004-08-30
申请人： Takeshi Nojima , 豪野嶋
发明人： NOJIMA TAKESHI
IPC分类号： G10D13/02 , G10D13/00
摘要： PROBLEM TO BE SOLVED: To realize a strainer of a snare drum with which a constitution is made simple, production cost is reduced and moreover, a tie up string mounted on the snare is simply tied up. SOLUTION: A lever 31, on which an approximately circular-arc shaped long hole is arranged, is supported by a supporting shaft 34 fixed on a plate shaped supporting member 11 in a freely rotatable manner. A columnar contactor 27 is engaged with the straight-line shaped long hole provided on the supporting member 11 and with the approximately circular-arc shaped long hole provided on the lever. A press-stopping plate 23 which press stops the tie-up string of the snare is mounted on a movable body 22 having an engaging section that engages with the groove provided on the supporting member 11 through screw bars 24a and 24b and round nuts 25a and 25b that screw into the screw bars 24a and 24b. A screw 21 which goes through the contactor 27 is screwed into the movable body 22 to link the contactor 27 and the movable body 22. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了实现简单的构造的小鼓的过滤器，制造成本降低，并且安装在圈套上的捆扎绳简单地被捆扎起来。解决方案：其上布置有大致圆弧形的长孔的杆31由可自由旋转的方式固定在板状支撑构件11上的支撑轴34支撑。圆柱形接触器27与设置在支撑构件11上的直线形长孔和设置在杠杆上的近似圆弧形的长孔接合。压紧止动板23将圈套的连结线卡止在具有接合部的移动体22上，该卡合部通过螺杆24a，24b与圆形螺母25a和 25b，螺钉进入螺杆24a和24b。穿过接触器27的螺钉21被拧入可移动体22中以连接接触器27和可移动体22.（C）2006年，JPO＆NCIPI

4. 发明授权

US5852570A Semiconductor memory using select transistors coupled to sub-bitlines from different blocks 失效
标题翻译：使用选择晶体管的半导体存储器，其耦合到来自不同块的子位线
公开(公告)号：US5852570A
公开(公告)日：1998-12-22
申请号：US866498
申请日：1997-05-30
申请人： Yasuhiro Hotta , Takeshi Nojima , Koji Komatsu
发明人： Yasuhiro Hotta , Takeshi Nojima , Koji Komatsu
IPC分类号： G11C17/00 , G11C16/04 , G11C16/06 , G11C17/12 , H01L21/8246 , H01L27/10 , H01L27/112
CPC分类号： G11C17/126 , H01L27/112
摘要： The semiconductor memory device of the invention includes: a semiconductor substrate; a first block; a second block adjacent to the first block; a main bitline; a first auxiliary conductive region; a first select transistor; and a first select line. The first block includes a first memory transistor having a first electrode, a second electrode and a gate electrode; a first sub-bitline including a part functioning as the first electrode of the first memory transistor; a second sub-bitline including a part functioning as the second electrode of the first memory transistor; and a first word line including a part functioning as the gate electrode of the first memory transistor, while the second block includes: a second memory transistor having a third electrode, a fourth electrode and a gate electrode; a third sub-bitline including a part functioning as the third electrode of the second memory transistor; a fourth sub-bitline including a part functioning as the fourth electrode of the second memory transistor; and a second word line including a part functioning as the gate electrode of the second memory transistor.
摘要翻译：本发明的半导体存储器件包括：半导体衬底; 第一块与第一块相邻的第二块; 主要位置第一辅助导电区域; 第一选择晶体管; 和第一选择线。第一块包括具有第一电极，第二电极和栅电极的第一存储晶体管; 第一子位线，包括用作第一存储晶体管的第一电极的部分; 第二子位线，包括用作第一存储晶体管的第二电极的部分; 以及第一字线，包括用作第一存储晶体管的栅电极的部分，而第二块包括：具有第三电极，第四电极和栅电极的第二存储晶体管; 第三子位线，包括用作第二存储晶体管的第三电极的部分; 第四子位线，包括用作第二存储晶体管的第四电极的部分; 以及包括用作第二存储晶体管的栅电极的部分的第二字线。

5. 发明授权

US06930922B2 Reading circuit, reference circuit, and semiconductor memory device 有权
标题翻译：读取电路，参考电路和半导体存储器件
公开(公告)号：US06930922B2
公开(公告)日：2005-08-16
申请号：US10630568
申请日：2003-07-29
申请人： Yasumichi Mori , Takahiko Yoshimoto , Shinsuke Anzai , Takeshi Nojima
发明人： Yasumichi Mori , Takahiko Yoshimoto , Shinsuke Anzai , Takeshi Nojima
IPC分类号： G11C16/06 , G11C7/00 , G11C11/56 , G11C16/02 , G11C16/04 , G11C16/28
CPC分类号： G11C11/5642 , G11C16/28 , G11C2211/5634
摘要： A reading circuit, for reading data from one memory cell of a plurality of memory cells, includes a plurality of division sensing circuits each connected to the one memory cell via a sensing line corresponding thereto among a plurality of sensing lines; and a current-voltage conversion circuit for converting a current flowing through each sensing line into a sensing voltage representing a potential of the corresponding sensing line. Each division sensing circuit includes a current load circuit for supplying a current to the one memory cell via a corresponding sensing line, and a sense amplifier for sensing a potential difference between the corresponding sensing line and a corresponding reference line of a plurality of reference lines. The current load circuit included in at least one division sensing circuit has a current supply capability different from that of the current load circuit included in another division sensing circuits.
摘要翻译：读取电路，用于从多个存储单元的一个存储单元读取数据，包括多个分割感测电路，每个分割感测电路经由多个感测线路中与之对应的感测线连接到该一个存储单元; 以及电流 - 电压转换电路，用于将流过每个感测线的电流转换成表示相应感测线的电位的感测电压。每个分割感测电路包括用于经由相应的感测线路向一个存储单元提供电流的电流负载电路和用于感测相应感测线与多条参考线的对应参考线之间的电位差的读出放大器。包括在至少一个分割感测电路中的电流负载电路具有与包括在另一个分割感测电路中的当前负载电路不同的电流供应能力。

6. 发明申请

US20050174859A1 Bias voltage applying circuit and semiconductor memory device 失效
标题翻译：偏置电压施加电路和半导体存储器件
公开(公告)号：US20050174859A1
公开(公告)日：2005-08-11
申请号：US11055641
申请日：2005-02-09
申请人： Yasumichi Mori , Takahiko Yoshimoto , Masahiko Watanabe , Shinsuke Anzai , Takeshi Nojima , Munetaka Masaki
发明人： Yasumichi Mori , Takahiko Yoshimoto , Masahiko Watanabe , Shinsuke Anzai , Takeshi Nojima , Munetaka Masaki
IPC分类号： G11C16/06 , G11C7/06 , G11C7/12 , G11C16/28 , G11C29/02 , G11C7/00 , G11C7/02
CPC分类号： G11C16/28 , G11C7/06 , G11C7/062 , G11C7/12 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/5004 , G11C2207/063
摘要： Two bias circuits which supply a current to a selected memory cell and a reference memory cell have the same circuit constitution. Each bias circuit includes a first active element between a power supply node and a junction node, where a current is controlled to prevent a voltage level at the junction node from fluctuating, a second active element between the power supply node and an output node, where a current is controlled such that a voltage level at the output node is changed in direction opposite to a voltage level at the junction node in other bias circuit, a third active element and a fourth active element between the junction node and a current supply node and between the output node and the current supply node, respectively, where a bias voltage is adjusted.
摘要翻译：向所选存储单元和参考存储单元提供电流的两个偏置电路具有相同的电路结构。每个偏置电路包括在电源节点和接合节点之间的第一有源元件，其中电流被控制以防止接合节点处的电压电平波动，电源节点和输出节点之间的第二有源元件，其中控制电流使得输出节点处的电压电平在与其他偏置电路中的连接节点处的电压电平相反的方向上改变，第三有源元件和第四有源元件在接合节点和电流供应节点之间，以及分别在输出节点和电流供应节点之间调整偏置电压。

7. 发明授权

US07088626B2 Bias voltage applying circuit and semiconductor memory device 失效
标题翻译：偏置电压施加电路和半导体存储器件
公开(公告)号：US07088626B2
公开(公告)日：2006-08-08
申请号：US11055641
申请日：2005-02-09
申请人： Yasumichi Mori , Takahiko Yoshimoto , Masahiko Watanabe , Shinsuke Anzai , Takeshi Nojima , Munetaka Masaki
发明人： Yasumichi Mori , Takahiko Yoshimoto , Masahiko Watanabe , Shinsuke Anzai , Takeshi Nojima , Munetaka Masaki
IPC分类号： G11C7/00
CPC分类号： G11C16/28 , G11C7/06 , G11C7/062 , G11C7/12 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/5004 , G11C2207/063
摘要： Two bias circuits which supply a current to a selected memory cell and a reference memory cell have the same circuit constitution. Each bias circuit includes a first active element between a power supply node and a junction node, where a current is controlled to prevent a voltage level at the junction node from fluctuating, a second active element between the power supply node and an output node, where a current is controlled such that a voltage level at the output node is changed in direction opposite to a voltage level at the junction node in other bias circuit, a third active element and a fourth active element between the junction node and a current supply node and between the output node and the current supply node, respectively, where a bias voltage is adjusted.
摘要翻译：向所选存储单元和参考存储单元提供电流的两个偏置电路具有相同的电路结构。每个偏置电路包括在电源节点和接合节点之间的第一有源元件，其中电流被控制以防止接合节点处的电压电平波动，电源节点和输出节点之间的第二有源元件，其中控制电流使得输出节点处的电压电平在与其他偏置电路中的连接节点处的电压电平相反的方向上改变，第三有源元件和第四有源元件在接合节点和电流供应节点之间，以及分别在输出节点和电流供应节点之间调整偏置电压。

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