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1. 发明授权

US4657630A Method for manufacturing semiconductor device having isolating groove 失效
标题翻译：具有隔离槽的半导体器件的制造方法
公开(公告)号：US4657630A
公开(公告)日：1987-04-14
申请号：US573322
申请日：1984-01-24
申请人： Takashi Agatsuma
发明人： Takashi Agatsuma
IPC分类号： H01L21/31 , H01L21/32 , H01L21/76 , H01L21/762 , H01L21/306 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L21/76205 , H01L21/32 , H01L21/76
摘要： A semiconductor device having a LOCOS region formed on a Si substrate comprises a minute groove filled with non-oxidizable isolation film provided at the boundary between the LOCOS region and an IC area to be formed on the Si substrate. The non-oxidizable isolation film prevents the intrusion of thermal oxidation for the LOCOS region into the IC region, and is of silicon nitride 1000-10000 .ANG. width.A method of manufacturing a semiconductor device having a LOCOS region formed on a Si substrate comprises the steps of depositing a silicon nitride film on the substrate; etching a minute width region at the boundary between an area to be the LOCOS region and an area to be an IC region on the substrate by anisotropic etching with a reactive ion etching mode, thereby to form a groove thereat thermal-oxidizing the Si substrate to form a thin SiO.sub.2 film on an area to be covered with silicon nitride; filling the groove with silicon nitride; thermal-oxidizing a part of the Si substrate other than the area covered with silicon nitride films formed previously; and removing the silicon nitride film deposited at the first step to flatten the surface of the Si substrate.
摘要翻译：具有形成在Si衬底上的LOCOS区域的半导体器件包括填充有在SiOS衬底上将要形成的LOCOS区域和IC区域之间的边界处的不可氧化隔离膜的微小沟槽。不可氧化的隔离膜防止LOCOS区域的热氧化侵入IC区域，并且氮化硅1000-10000安培宽度。制造在Si衬底上形成有LOCOS区域的半导体器件的方法包括以下步骤：在衬底上沉积氮化硅膜; 在反应离子蚀刻模式下通过各向异性蚀刻在基板上的作为LOCOS区域的区域和作为IC区域的区域之间的边界处蚀刻微小宽度区域，从而在Si基板上热氧化Si基板在被氮化硅覆盖的区域上形成薄的SiO 2膜; 用氮化硅填充槽; 热氧化除了先前形成的氮化硅膜覆盖的区域之外的Si衬底的一部分; 以及去除在第一步骤沉积的氮化硅膜以使Si衬底的表面变平。

2. 发明授权

US4258379A IIL With in and outdiffused emitter pocket 失效
标题翻译： IIL带有进出口的发射器口袋
公开(公告)号：US4258379A
公开(公告)日：1981-03-24
申请号：US78452
申请日：1979-09-24
申请人： Tomoyuki Watanabe , Takahiro Okabe , Minoru Nagata , Tohru Nakamura , Kenji Kaneko , Yutaka Okada , Norio Anzai , Takanori Nishimura , Takashi Agatsuma
发明人： Tomoyuki Watanabe , Takahiro Okabe , Minoru Nagata , Tohru Nakamura , Kenji Kaneko , Yutaka Okada , Norio Anzai , Takanori Nishimura , Takashi Agatsuma
IPC分类号： H01L21/74 , H01L21/761 , H01L21/8226 , H01L27/02 , H01L27/04 , H03K19/091
CPC分类号： H01L21/74 , H01L21/761 , H01L21/8226 , H01L27/0244
摘要： A semiconductor IC device in which an N-type semiconductor layer is formed in a P-type semiconductor substrate; the N-type layer is divided by a P.sup.+ -type insulation region into plural island regions; and an IIL is formed in a first island region while an NPN transistor is formed in a second island region, wherein an N-type up-diffused layer is formed from the bottom of the first island region up while an N-type well region is formed from the surface of the first island region down, and N.sup.+ -type buried layers are formed near the bottoms of the first and the second island region.
摘要翻译：一种在P型半导体衬底中形成N型半导体层的半导体IC器件; N型层被P +型绝缘区划分成多个岛状区域; 并且在第一岛状区域中形成IIL，而在第二岛状区域中形成NPN晶体管，其中N型上扩散层从第一岛区的底部向上形成，而N型阱区为从第一岛区域的表面向下形成，并且在第一岛区域和第二岛区域的底部附近形成N +型掩埋层。

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