专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08583968B2 Data storage apparatus and method for writing data 失效
标题翻译：用于写入数据的数据存储装置和方法
公开(公告)号：US08583968B2
公开(公告)日：2013-11-12
申请号：US13087177
申请日：2011-04-14
申请人： Takami Sugita , Hiroyuki Moro , Takahiro Nango
发明人： Takami Sugita , Hiroyuki Moro , Takahiro Nango
IPC分类号： G06F11/00
CPC分类号： G06F11/1048 , G11C2029/0411
摘要： According to one embodiment, a data storage apparatus includes a read module, an error detector and a controller. The read module is configured to read data from a flash memory, more precisely from a rewrite area and a write-back area, both provided in the flash memory. The error detector is configured to detect errors, if any, in the data read. The controller is configured to keep rewriting data, without correcting the errors the error detector has detected in the rewrite area of the flash memory.
摘要翻译：根据一个实施例，数据存储装置包括读取模块，错误检测器和控制器。读取模块被配置为从闪速存储器中更准确地读取来自闪存中的重写区域和回写区域的数据。错误检测器被配置为检测数据读取中的错误（如果有的话）。控制器被配置为保持重写数据，而不纠正错误检测器在闪存的重写区域中检测到的错误。

2. 发明授权

US06775731B2 Computer system with extension unit connected to peripheral equipment 失效
标题翻译：具有扩展单元的计算机系统连接到外围设备
公开(公告)号：US06775731B2
公开(公告)日：2004-08-10
申请号：US09788401
申请日：2001-02-21
申请人： Takami Sugita
发明人： Takami Sugita
IPC分类号： G06F300
CPC分类号： G06F13/387
摘要： Among plural types of signals sent/received between a computer (PC) and a extension unit (extension adapter), a predetermined signal group is converted to a serial data and delivered through a serial bus, and a specific signal directly affecting the operational-speed is directly delivered through a direct signal line so that the number of connection signals between the computer and the extension unit is reduced while keeping the operational-speed from lowering, a connector can be made smaller, and the device constitution of the entire system can be compact.
摘要翻译：在计算机（PC）和扩展单元（扩展适配器）之间发送/接收的多种类型的信号中，预定信号组被转换为串行数据并通过串行总线传送，并且直接影响操作速度的特定信号通过直接信号线直接传送，从而减少计算机与扩展单元之间的连接信号数量，同时保持操作速度降低，可以使连接器更小，并且整个系统的设备结构可以紧凑。

3. 发明申请

US20110153927A1 Storage Control Device, Electronic Device, and Storage Control Method 审中-公开
标题翻译：存储控制装置，电子装置和存储控制方法
公开(公告)号：US20110153927A1
公开(公告)日：2011-06-23
申请号：US12878604
申请日：2010-09-09
申请人： Takami SUGITA
发明人： Takami SUGITA
IPC分类号： G06F12/00
CPC分类号： G09G5/393 , G09G5/18 , G09G2360/10 , G09G2360/128 , H04N21/426
摘要： According to one embodiment, a storage control device includes a controller, a detector, and a refreshing module. The controller writes image data, which is to be output to a display module, to a storage device and outputs the image data from the storage device to the display module. The detector detects a blanking period during which the controller does not write the image data to the storage device and does not output the image data from the storage device to the display module. The refreshing module refreshes the storage device by rewriting the image data to the storage device at a predetermined time interval if the detector detects a blanking period.
摘要翻译：根据一个实施例，存储控制装置包括控制器，检测器和刷新模块。控制器将要输出到显示模块的图像数据写入存储装置，并将图像数据从存储装置输出到显示模块。检测器检测到控制器不将图像数据写入存储装置的消隐期间，并且不将图像数据从存储装置输出到显示模块。如果检测器检测到消隐期，则刷新模块通过将图像数据以预定时间间隔重写到存储设备来刷新存储设备。

4. 发明申请

US20110320868A1 DATA STORAGE APPARATUS AND METHOD FOR WRITING DATA 失效
标题翻译：数据存储设备和数据写入方法
公开(公告)号：US20110320868A1
公开(公告)日：2011-12-29
申请号：US13087177
申请日：2011-04-14
申请人： Takami SUGITA , Hiroyuki MORO , Takahiro NANGO
发明人： Takami SUGITA , Hiroyuki MORO , Takahiro NANGO
IPC分类号： G06F11/07
CPC分类号： G06F11/1048 , G11C2029/0411
摘要： According to one embodiment, a data storage apparatus includes a read module, an error detector and a controller. The read module is configured to read data from a flash memory, more precisely from a rewrite area and a write-back area, both provided in the flash memory. The error detector is configured to detect errors, if any, in the data read. The controller is configured to keep rewriting data, without correcting the errors the error detector has detected in the rewrite area of the flash memory.
摘要翻译：根据一个实施例，数据存储装置包括读取模块，错误检测器和控制器。读取模块被配置为从闪速存储器中更准确地读取来自闪存中的重写区域和回写区域的数据。错误检测器被配置为检测数据读取中的错误（如果有的话）。控制器被配置为保持重写数据，而不纠正错误检测器在闪存的重写区域中检测到的错误。

5. 发明申请

US20070130435A1 Terminal apparatus and its data management method 审中-公开
标题翻译：终端设备及其数据管理方法
公开(公告)号：US20070130435A1
公开(公告)日：2007-06-07
申请号：US11543147
申请日：2006-10-05
申请人： Takami Sugita
发明人： Takami Sugita
IPC分类号： G06F12/14
CPC分类号： G06F21/6245 , G06F2221/2141 , G06F2221/2143 , H04M1/72519
摘要： A terminal apparatus is provided with a memory, a communication section, an authentication section configured to execute authentication when a signal requesting access to the memory is received, a save processing section configured to save predetermined data of the memory in a predetermined storage section when the authentication section outputs a negative result, and an erasing section configured to erase the predetermined data from the memory after the predetermined data is saved.
摘要翻译：终端装置具有存储器，通信部，认证部，被配置为当接收到请求存取存储器的信号时执行认证;保存处理部，被配置为当存储器的预定数据保存在预定的存储部中时，验证部分输出否定结果，以及擦除部分，被配置为在保存预定数据之后从存储器擦除预定数据。

6. 发明申请

US20060179180A1 Signal processing apparatus, signal processing system and signal processing method 审中-公开
标题翻译：信号处理装置，信号处理系统及信号处理方法
公开(公告)号：US20060179180A1
公开(公告)日：2006-08-10
申请号：US11337507
申请日：2006-01-24
申请人： Takami Sugita , Minoru Moriwaki
发明人： Takami Sugita , Minoru Moriwaki
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： An apparatus includes a first direct memory access controller which successively processes first descriptors, thereby executing a series of data transfers for reading first data, which is stored in a memory, and generates an activation signal in a case where a current to-be-processed first descriptor of the first descriptors includes control information which instructs start of another data transfer, a second direct memory access controller which executes, each time the activation signal is received, a current to-be-processed second descriptor of second descriptors, thereby executing one of a series of data transfers for reading second data, which is stored in the memory, and an output signal generation unit that mixes the first data which is read by the first direct memory access controller and the second data which is read by the second direct memory access controller, thereby generating an output signal including the first data and the second data.
摘要翻译：一种装置包括连续处理第一描述符的第一直接存储器访问控制器，从而执行一系列用于读取存储在存储器中的第一数据的数据传输，并且在待处理的电流的情况下产生激活信号第一描述符的第一描述符包括指示另一数据传送开始的控制信息，每次接收到激活信号时执行的第二直接存储器访问控制器，第二描述符的当前被处理的第二描述符，从而执行一个用于读取存储在存储器中的第二数据的一系列数据传输;以及输出信号生成单元，其将由第一直接存储器访问控制器读取的第一数据和由第二直接存取控制器读取的第二数据进行混合存储器访问控制器，从而生成包括第一数据和第二数据的输出信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式