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1. 发明授权

US4356481A Source voltage drop detecting circuit 失效
标题翻译：源压降检测电路
公开(公告)号：US4356481A
公开(公告)日：1982-10-26
申请号：US138948
申请日：1980-04-09
申请人： Takakuni Kuki
发明人： Takakuni Kuki
IPC分类号： G01R19/165 , G01R31/36 , H02H3/24 , H02J7/00 , G08B21/00 , G01R19/16
CPC分类号： G01R15/04 , G01R19/16542
摘要： A voltage drop detection circuit provides an accurate indication of battery voltage in an apparatus subject to large fluctuations in load current regardless of the battery internal resistance. The detection circuit periodically induces an increase in load current so as to reproduce the maximum load current drawn by the apparatus, and the resulting battery terminal voltage is compared to a fixed reference. The detection circuit finds particular utility in apparatus designed to use a variety of battery types.
摘要翻译：电压降检测电路提供负载电流大的波动的装置中的电池电压的精确指示，而与电池内阻无关。检测电路周期性地引起负载电流的增加，以便再现由该装置吸收的最大负载电流，并且将所得到的电池端子电压与固定基准进行比较。检测电路在设计用于使用各种电池类型的设备中具有特殊的用途。

2. 发明授权

US5652752A Mobile radio communication system employing time division multiple transmission scheme 失效
标题翻译：移动无线通信系统采用时分多址传输方案
公开(公告)号：US5652752A
公开(公告)日：1997-07-29
申请号：US406478
申请日：1995-03-20
申请人： Toshiro Suzuki , Arata Nakagoshi , Takao Harakawa , Izumi Horikawa , Takakuni Kuki
发明人： Toshiro Suzuki , Arata Nakagoshi , Takao Harakawa , Izumi Horikawa , Takakuni Kuki
IPC分类号： H04B7/26 , H04W48/12 , H04W72/12 , H04B7/212
CPC分类号： H04W84/20 , H04B7/2643 , H04W48/12
摘要： In a mobile radio communication system employing a time-division multiple transmission scheme, having a plurality of base stations and a plurality of personal stations, an arbitrary base station, when detecting a pilot signal transmitted from any master base station in the mobile radio communication system, acts as a slave base station which does not transmit its pilot signal but transmits and receives a common control signal to and from a personal station utilizing a frequency channel occupied by the pilot signal. On the other hand, when not receiving the pilot signal, the base station searches for an available frequency channel, and acts as a master base station which transmits its pilot signal on the available frequency channel to occupy the frequency channel, and transmits and receives the common control signal to and from a personal station on that frequency channel.
摘要翻译：在使用具有多个基站和多个个人站的时分多路传输方式的移动无线通信系统中，任意基站在检测到移动无线通信系统中的任何主基站发送的导频信号时作为不发送其导频信号的从基站，利用由导频信号占用的频道来发送和接收来自个人站的公共控制信号。另一方面，在没有接收到导频信号的情况下，基站搜索可用的频道，作为在可用频率信道上发送其导频信号的主基站，占据频道，并发送和接收与该频道上的个人站的通用控制信号。

3. 发明授权

US4167701A Decoder for error-correcting code data 失效
标题翻译：解码器用于纠错码数据
公开(公告)号：US4167701A
公开(公告)日：1979-09-11
申请号：US844942
申请日：1977-10-25
申请人： Takakuni Kuki , Hiroyuki Tatsumi
发明人： Takakuni Kuki , Hiroyuki Tatsumi
IPC分类号： H03M13/00 , H04L1/00 , H04L1/02 , H04L1/20 , H03K13/32
CPC分类号： H04L1/20 , H04L1/0045
摘要： An error correcting decoder is disclosed which blocks correction of bits received during periods of relatively high signal intensity levels. A syndrome register and decision circuit provide error correcting bits for all bits which the sequence of input data determines to be in error. But only those data bits which occur during low levels of signal intensity are corrected.
摘要翻译：公开了一种纠错解码器，其阻止在相对高的信号强度级别的周期期间接收的比特的校正。校正子寄存器和判定电路为输入数据序列确定为错误的所有位提供纠错位。但只有在低信号强度水平下发生的那些数据位被校正。

4. 发明授权

US4502141A Circuit for checking bit errors in a received BCH code succession by the use of primitive and non-primitive polynomials 失效
标题翻译：通过使用原始和非原始多项式来检查接收的BCH码序列中的比特错误的电路
公开(公告)号：US4502141A
公开(公告)日：1985-02-26
申请号：US415873
申请日：1982-09-08
申请人： Takakuni Kuki
发明人： Takakuni Kuki
IPC分类号： H03M13/00 , H03M13/15 , G06F11/10
CPC分类号： H03M13/15
摘要： For use in deciding whether a single or a t-tuple error (t being greater than unity) is present in each bit sequence given as a primitive BCH code in accordance with a generator polynomial comprising a primitive and a non-primitive polynomial, an error checking circuit comprises first and second dividers (16, 17) for dividing each bit sequence by the primitive and the non-primitive polynomials to provide first and second signals, respectively. If the bit sequence includes only a single error, the first signal represents one of non-zero residues which result by the division when such single errors are present at the respective bit locations of the sequence. A memory (18) is preliminarily loaded with reference numbers corresponding to the respective non-zero residues and produces one of the reference numbers in response to the first signal only in the presence of a single error. A comparator (19) compares the produced reference number with a residue represented by the second signal to carry out the decision. Preferably, the memory is loaded also with the single error bit locations to locate the single error in a bit sequence being checked. The circuit may be a microcomputer operable in the above-described manner.
摘要翻译：为了用于根据包括原始和非原始多项式的生成多项式来确定作为原始BCH码给出的每个比特序列中是否存在单个或一个t元组错误（t大于一个），错误检查电路包括第一和第二分频器（16,17），用于将每个比特序列除以原语和非原始多项式，以分别提供第一和第二信号。如果比特序列仅包括单个错误，则当在序列的相应比特位置存在这样的单个错误时，第一个信号表示通过除法产生的非零残基之一。存储器（18）预先加载与各个非零残差相对应的附图标记，并且仅在存在单一误差的情况下响应于第一信号而产生一个附图标记。比较器（19）将产生的参考数与由第二信号表示的残差进行比较，以执行该决定。优选地，存储器也加载有单个错误位位置，以在正在检查的位序列中定位单个错误。电路可以是以上述方式可操作的微型计算机。

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