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1. 发明申请

US20090315604A1 CLOCK SIGNAL GENERATION APPARATUS AND DISCRETE-TIME CIRCUIT 审中-公开
标题翻译：时钟信号发生装置和分离电路
公开(公告)号：US20090315604A1
公开(公告)日：2009-12-24
申请号：US12483640
申请日：2009-06-12
申请人： Taiji AKIZUKI , Masahiko SAGISAKA , Hisashi ADACHI
发明人： Taiji AKIZUKI , Masahiko SAGISAKA , Hisashi ADACHI
IPC分类号： H03K3/00
CPC分类号： H03K5/135 , H03K5/133 , H03K5/1515 , H03K2005/00234
摘要： In a clock signal generation apparatus, a clock signal delay calculation section has a delay detection circuit for monitoring the delay characteristics of the variable delay circuits of a clock signal generation circuit due to external variation factors and calculates the delay amounts of N-phase clock signals, and a clock signal delay control section varies the delay amounts of the variable delay circuits on the basis of delay variation data, external variation factors being used as parameters thereof, stored in a delay variation data section and the calculated delay amounts of the N-phase clock signals. In the case that, for example, clock signals required for a discrete-time circuit have changed due to external variation factors, such as power supply voltage and environmental temperature, the non-overlap times and the duty ratios of the clock signals required for the discrete-time circuit can be set to optimal values.
摘要翻译：在时钟信号发生装置中，时钟信号延迟计算部分具有延迟检测电路，用于监视由于外部变化因素引起的时钟信号发生电路的可变延迟电路的延迟特性，并计算N相时钟信号的延迟量并且时钟信号延迟控制部分根据存储在延迟变化数据部分中的延迟变化数据，用作其参数的外部变化因子和所计算的延迟量的延迟量来改变可变延迟电路的延迟量，相位时钟信号。在例如离散时间电路所需的时钟信号由于诸如电源电压和环境温度之类的外部变化因素而改变的情况下，所需的时钟信号的非重叠时间和占空比离散时间电路可以设置为最佳值。

2. 发明授权

US07515080B2 A/D converter 失效
标题翻译： A / D转换器
公开(公告)号：US07515080B2
公开(公告)日：2009-04-07
申请号：US11898644
申请日：2007-09-13
申请人： Taiji Akizuki , Tomoaki Maeda , Hisashi Adachi
发明人： Taiji Akizuki , Tomoaki Maeda , Hisashi Adachi
IPC分类号： H03M3/00
CPC分类号： H03M1/0854 , H03M1/362
摘要： An A/D converter includes a first switched capacitor block that charges and holds charges by connecting each of a first group of capacitors to a single basic reference voltage at a first timing, and discharges each of the charges held by the first group of capacitors at a second timing, a second switched capacitor block that charges and holds each of the charges discharged by the first group of capacitors respectively in the second group of capacitors at the second timing, and converts each of the charges held by the second group of capacitors to a voltage and outputs the voltages at the first timing, and a quantizer that quantizes an analog input signal using the plurality of voltages output from the second switched capacitor block as reference voltages for each level. A plurality of reference voltages is generated from a single basic reference voltage, based on different amounts of charges held in the plurality of capacitors. A high SNR is obtained by supplying the reference voltages of a quantizer in a multi-bit A/D converter with high accuracy, and low power consumption operation is possible with simplified circuitry.
摘要翻译： A / D转换器包括第一开关电容器块，其通过在第一定时将第一组电容器连接到单个基准参考电压来充电并保持电荷，并且将由第一组电容器保持的每个电荷放电第二定时，第二开关电容器块，其在第二定时将第一组电容器中的第一组电容器分别充电并保持每个电荷，并将由第二组电容器保持的每个电荷转换为电压并在第一定时输出电压;以及量化器，其使用从第二开关电容器块输出的多个电压量化模拟输入信号作为每个电平的参考电压。基于保持在多个电容器中的不同电荷量，从单个基准参考电压产生多个参考电压。通过在多位A / D转换器中提供高精度的量化器的参考电压来获得高信噪比，并且通过简化的电路可以实现低功耗操作。

3. 发明申请

US20080252502A1 DELTA-SIGMA AD CONVERTER APPARATUS USING DELTA-SIGMA MODULATOR CIRCUIT PROVIDED WITH RESET CIRCUIT RESETTING INTEGRATOR 失效
标题翻译：使用复位电路复位整流器提供的DELTA-SIGMA调制器电路的DELTA-SIGMA AD转换器
公开(公告)号：US20080252502A1
公开(公告)日：2008-10-16
申请号：US12100236
申请日：2008-04-09
申请人： Tomoaki Maeda , Taiji Akizuki , Hisashi Adachi
发明人： Tomoaki Maeda , Taiji Akizuki , Hisashi Adachi
IPC分类号： H03M3/02
CPC分类号： H03M3/364 , H03M3/424
摘要： In a delta-sigma modulator circuit, an integrator integrates an input signal, and a quantization circuit quantizes the integrated signal with a predetermined quantization number, and outputs a quantization result signal. A DA converter circuit outputs an analog signal indicating a DA conversion result based on the quantization result signal. An oscillation detector circuit detects that the integrator is in an oscillation state based on the integrated signal, and outputting an oscillation detection signal. A reset circuit resets the integrator based on the oscillation detection signal.
摘要翻译：在Δ-Σ调制器电路中，积分器对输入信号进行积分，并且量化电路以预定量化数量化积分信号，并输出量化结果信号。 DA转换器电路基于量化结果信号输出表示DA转换结果的模拟信号。振荡检测器电路基于积分信号检测积分器处于振荡状态，并输出振荡检测信号。复位电路基于振荡检测信号复位积分器。

4. 发明申请

US20050215209A1 Transmitter 失效
标题翻译：发射机
公开(公告)号：US20050215209A1
公开(公告)日：2005-09-29
申请号：US11085459
申请日：2005-03-22
申请人： Mitsuru Tanabe , Taiji Akizuki , Koichiro Tanaka
发明人： Mitsuru Tanabe , Taiji Akizuki , Koichiro Tanaka
IPC分类号： H04J11/00 , H01Q11/12 , H03F1/02 , H03F1/32 , H03F3/38 , H04B1/02 , H04B1/04
CPC分类号： H03F1/0211 , H03F1/02 , H03F1/0227 , H03F1/0277 , H03F1/32 , H03F3/24 , H03F2200/511 , H04B2001/045
摘要： An amplitude component and a phase component of a modulated signal are inputted into a power supply terminal and an input terminal of an RF power amplifier, respectively, and a modulated wave that is produced by demodulating an original modulated signal is obtained from the RF power amplifier. A supply voltage is supplied to an emitter follower and an operational amplifier via a switch group from a DC-DC converter group whose output voltages are sequentially different. As the supply voltage, any pair of outputs of DC-DC converters by the switch group is selected according to levels of the amplitude component, and provides them to the emitter follower and the operational amplifier. The emitter follower performs a DC conversion of the provided supply voltage to provide it to the RF power amplifier.
摘要翻译：调制信号的幅度分量和相位分量分别输入到RF功率放大器的电源端子和输入端子，并且从RF功率放大器获得通过解调原始调制信号产生的调制波。电源电压经由输出电压依次不同的DC-DC转换器组经由开关组提供给发射极跟随器和运算放大器。作为电源电压，根据振幅分量的电平选择开关组的DC-DC转换器的任何一对输出，并将其提供给射极跟随器和运算放大器。射极跟随器对所提供的电源电压进行DC转换，以将其提供给RF功率放大器。

5. 发明授权

US08891697B2 Reception signal processing device 有权
标题翻译：接收信号处理装置
公开(公告)号：US08891697B2
公开(公告)日：2014-11-18
申请号：US13816076
申请日：2012-02-23
申请人： Masashi Kobayashi , Suguru Fujita , Taiji Akizuki
发明人： Masashi Kobayashi , Suguru Fujita , Taiji Akizuki
IPC分类号： H04L27/08 , H03F3/45 , H03F1/02 , H04B1/30 , H03G3/30 , H03F3/72 , H03F3/189 , H04L25/06
CPC分类号： H04L25/06 , H03F1/0277 , H03F3/189 , H03F3/45183 , H03F3/45748 , H03F3/72 , H03F2200/294 , H03F2200/336 , H03F2200/405 , H03F2200/411 , H03F2200/507 , H03F2203/45212 , H03F2203/45352 , H03F2203/45702 , H03F2203/7215 , H03F2203/7221 , H03F2203/7227 , H03F2203/7231 , H03F2203/7236 , H03G3/3068 , H04B1/30
摘要： A reception signal processing devices includes a converter which converts an analog signal amplified by an amplifying section to a digital signal, switches respectively provided in post-stages of variable gain amplifiers of the amplifying section, a bypass switch section which sets to open and close a path in which outputs of the variable gain amplifiers go around the variable gain amplifiers of the post-stages and are inputted to the converter, a switch controller which controls the switches and the bypass switch section and a DC offset controller which sets a correction value of a DC offset in accordance with a gain set to the variable gain amplifier as an object to be corrected.
摘要翻译：接收信号处理装置包括将由放大部分放大的模拟信号转换为数字信号的转换器，分别设置在放大部分的可变增益放大器的后级中的开关，设置为打开和关闭的旁路开关部分可变增益放大器的输出绕过后级的可变增益放大器并且被输入到转换器的路径，控制开关和旁路开关部分的开关控制器和设置校正值的DC偏移控制器根据作为要校正对象的可变增益放大器设定的增益的DC偏移。

6. 发明申请

US20130136213A1 RECEPTION SIGNAL PROCESSING DEVICE 有权
标题翻译：接收信号处理装置
公开(公告)号：US20130136213A1
公开(公告)日：2013-05-30
申请号：US13816076
申请日：2012-02-23
申请人： Masashi Kobayashi , Suguru Fujita , Taiji Akizuki
发明人： Masashi Kobayashi , Suguru Fujita , Taiji Akizuki
IPC分类号： H04L25/06
CPC分类号： H04L25/06 , H03F1/0277 , H03F3/189 , H03F3/45183 , H03F3/45748 , H03F3/72 , H03F2200/294 , H03F2200/336 , H03F2200/405 , H03F2200/411 , H03F2200/507 , H03F2203/45212 , H03F2203/45352 , H03F2203/45702 , H03F2203/7215 , H03F2203/7221 , H03F2203/7227 , H03F2203/7231 , H03F2203/7236 , H03G3/3068 , H04B1/30
摘要： A reception signal processing devices includes a converter which converts an analog signal amplified by an amplifying section to a digital signal, switches respectively provided in post-stages of variable gain amplifiers of the amplifying section, a bypass switch section which sets to open and close a path in which outputs of the variable gain amplifiers go around the variable gain amplifiers of the post-stages and are inputted to the converter, a switch controller which controls the switches and the bypass switch section and a DC offset controller which sets a correction value of a DC offset in accordance with a gain set to the variable gain amplifier as an object to be corrected.
摘要翻译：接收信号处理装置包括将由放大部分放大的模拟信号转换为数字信号的转换器，分别设置在放大部分的可变增益放大器的后级中的开关，设置为打开和关闭的旁路开关部分可变增益放大器的输出绕过后级的可变增益放大器并且被输入到转换器的路径，控制开关和旁路开关部分的开关控制器和设置校正值的DC偏移控制器根据作为要校正对象的可变增益放大器设定的增益的DC偏移。

7. 发明申请

US20130127650A1 A/D CONVERSION DEVICE 有权
标题翻译： A / D转换器件
公开(公告)号：US20130127650A1
公开(公告)日：2013-05-23
申请号：US13814205
申请日：2012-03-21
申请人： Taiji Akizuki , Suguru Fujita
发明人： Taiji Akizuki , Suguru Fujita
IPC分类号： H03M1/20
CPC分类号： H03M1/20 , H03M1/201
摘要： An A/D conversion device has means for generating a control clock signal having a cycle that is an integral multiple of a cycle of a reference clock signal; means for generating a shift voltage which varies every cycle of the reference clock signal while the cycle of the control clock signal is taken as one cycle, means for offsetting an analog signal by the shift voltage, means for A/D converting the offset analog signal every cycle of the reference clock signal signal, and means for averaging outputs from the A/D converter every cycle of the control clock signal.
摘要翻译： A / D转换装置具有用于产生具有作为参考时钟信号的周期的整数倍的周期的控制时钟信号的装置; 用于产生在控制时钟信号的周期作为一个周期的基准时钟信号的每个周期变化的移位电压的装置，用于通过移位电压偏移模拟信号的装置，用于对偏移模拟信号进行A / D转换的装置参考时钟信号信号的每个周期，以及用于对来自A / D转换器的每个周期的控制时钟信号的输出进行平均的装置。

8. 发明授权

US07515079B2 Method of controlling delta-sigma modulator and delta-sigma modulator 有权
标题翻译：控制Δ-Σ调制器和Δ-Σ调制器的方法
公开(公告)号：US07515079B2
公开(公告)日：2009-04-07
申请号：US11896816
申请日：2007-09-06
申请人： Tomoaki Maeda , Hisashi Adachi , Taiji Akizuki
发明人： Tomoaki Maeda , Hisashi Adachi , Taiji Akizuki
IPC分类号： H03M3/00
CPC分类号： H03M3/374 , H03M3/43 , H03M3/448 , H03M3/454
摘要： To provide a method of controlling a delta-sigma modulator and a delta-sigma modulator capable of suppressing a consumption power and also improving a signal-to-noise ratio by implementing both the zero-point shifting technology and the double sampling technology simultaneously, a delta-sigma modulator includes a first integrator (1), a second integrator (2), a third integrator (3), a local feedback (4), delay units (5), a quantizer (6), a DA converter (7), gains (8a to 8c) of the DA converter, gains (9a to 9c) of the integrators, adders (10), no-delay integrators (11) each having a gain “1”, a gain (12) of the local feedback, a DAC (13) of a gain “1”, a delay unit (5) for delaying output signals of the DA converter (7), and a delay unit (5) for delaying an output signal of the local feedback (4).
摘要翻译：为了提供一种通过同时实现零点移位技术和双重采样技术来控制能够抑制消耗功率并且还提高信噪比的Δ-Σ调制器和Δ-Σ调制器的方法， Δ-Σ调制器包括第一积分器（1），第二积分器（2），第三积分器（3），局部反馈（4），延迟单元（5），量化器（6），DA转换器），DA转换器的增益（8a至8c），增益（9a至9c）的积分器，加法器（10），无延迟积分器（11），每个均具有增益“1”，增益（12）本地反馈，增益“1”的DAC（13），用于延迟DA转换器（7）的输出信号的延迟单元（5），以及用于延迟本地反馈的输出信号的延迟单元（5） 4）。

9. 发明授权

US07466257B2 Delta-sigma AD converter 失效
公开(公告)号：US07466257B2
公开(公告)日：2008-12-16
申请号：US11898645
申请日：2007-09-13
申请人： Taiji Akizuki , Tomoaki Maeda , Hisashi Adachi
发明人： Taiji Akizuki , Tomoaki Maeda , Hisashi Adachi
IPC分类号： H03M3/00
CPC分类号： H03M3/47
摘要： The output of a first integrator is quantized in a quantizer. The quantized signal is subjected to D/A conversion, successively output to a plurality of output paths by a first switching circuit, sampled and held by a plurality of charge-holding circuits of a first feedback circuit, and successively output by a second switching circuit to one of the input terminals of a subtractor. On the other hand, the output signal of the first integrator is successively output by a third switching circuit to a plurality of output paths, sampled and held by a plurality of charge-holding circuits of a second feedback circuit, and successively input to the other input terminal of the subtractor by a fourth switching circuit along with signals held in an input portion, which samples and holds input analog signals. By doing so, a plurality of signals with different sampling timings are integrated accumulatively by the subtractor and the first integrator. When integration functions used to obtain an n-th order noise-shaping effect are multiplexed and operated using a single integrator, the integrator's current consumption can be suppressed.

10. 发明授权

US07395039B2 Transmitter 有权
标题翻译：发射机
公开(公告)号：US07395039B2
公开(公告)日：2008-07-01
申请号：US11282597
申请日：2005-11-21
申请人： Taiji Akizuki , Mitsuru Tanabe
发明人： Taiji Akizuki , Mitsuru Tanabe
IPC分类号： H01Q11/12 , H03C1/62
CPC分类号： H03G3/3042 , H03C5/00 , H04L27/2626
摘要： In a transmitter of the present invention, a modulated signal is separated into an amplitude component and a phase component which are inputted to a radio-frequency modulated signal input terminal and a supply voltage terminal of a radio-frequency power amplifier. A voltage adjustment circuit is provided between an output terminal of the radio-frequency power amplifier and an amplitude amplification circuit having a feedback circuit. The voltage adjustment circuit changes the amount of isolation in accordance with the voltage level of the amplitude component. By this, the amplitude component of the radio-frequency modulated wave attenuates the level inputted to the feedback circuit of the amplitude amplification circuit through the supply voltage terminal of the radio-frequency power amplifier.
摘要翻译：在本发明的发送机中，将调制信号分离为输入到射频功率放大器的射频调制信号输入端子和电源电压端子的振幅分量和相位分量。在高频功率放大器的输出端子和具有反馈电路的振幅放大电路之间设置电压调节电路。电压调节电路根据振幅分量的电压电平来改变隔离度。由此，射频调制波的幅度分量通过射频功率放大器的电源电压衰减输入到幅度放大电路的反馈电路的电平。

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