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1. 发明授权

US09135009B2 Apparatus and method for compressing instructions and a computer-readable storage media therefor 有权
标题翻译：用于压缩指令的装置和方法及其计算机可读存储介质
公开(公告)号：US09135009B2
公开(公告)日：2015-09-15
申请号：US13595198
申请日：2012-08-27
申请人： Tai-Song Jin
发明人： Tai-Song Jin
IPC分类号： G06F9/38 , G06F9/30 , G06F9/00
CPC分类号： G06F9/30178 , G06F9/3822
摘要： Provided is a technique that is capable of efficiently compressing instructions by inserting instruction compression bits into valid instruction bundles and deleting no operation (NOP) instruction bundles. Accordingly, the number of instructions that can be parallel-processed in a processor may be increased.
摘要翻译：提供了一种能够通过将指令压缩比特插入有效指令束并且不删除无操作（NOP）指令束）来有效地压缩指令的技术。因此，可以增加可以在处理器中并行处理的指令的数量。

2. 发明授权

US08930929B2 Reconfigurable processor and method for processing a nested loop 有权
标题翻译：可重构处理器和处理嵌套循环的方法
公开(公告)号：US08930929B2
公开(公告)日：2015-01-06
申请号：US13086629
申请日：2011-04-14
申请人： Min-Wook Ahn , Dong-Hoon Yoo , Jin-Seok Lee , Bernhard Egger , Tai-Song Jin , Won-Sub Kim , Hee-Jin Ahn
发明人： Min-Wook Ahn , Dong-Hoon Yoo , Jin-Seok Lee , Bernhard Egger , Tai-Song Jin , Won-Sub Kim , Hee-Jin Ahn
IPC分类号： G06F9/45 , G06F9/50
CPC分类号： G06F9/5066
摘要： A reconfigurable processor which merges an inner loop and an outer loop which are included in a nested loop and allocates the merged loop to processing elements in parallel, thereby reducing processing time to process the nested loop. The reconfigurable processor may extract loop execution frequency information from the inner loop and the outer loop of the nested loop, and may merge the inner loop and the outer loop based on the extracted loop execution frequency information.
摘要翻译：一种可重构的处理器，它将包含在嵌套循环中的内循环和外循环合并，并行地将合并循环分配给处理元素，从而减少了处理嵌套循环的处理时间。可重配置处理器可以从嵌套循环的内循环和外循环提取循环执行频率信息，并且可以基于提取的循环执行频率信息合并内循环和外循环。

3. 发明申请

US20120246444A1 RECONFIGURABLE PROCESSOR, APPARATUS, AND METHOD FOR CONVERTING CODE 审中-公开
标题翻译：可重构处理器，装置和转换代码的方法
公开(公告)号：US20120246444A1
公开(公告)日：2012-09-27
申请号：US13362363
申请日：2012-01-31
申请人： Tai-Song Jin , Dong-Hoon Yoo , Min-Wook Ahn , Jin-Seok Lee
发明人： Tai-Song Jin , Dong-Hoon Yoo , Min-Wook Ahn , Jin-Seok Lee
IPC分类号： G06F15/80 , G06F9/06
CPC分类号： G06F15/7892 , G06F8/4452 , G06F8/451 , G06F9/30054 , G06F9/30076 , G06F9/30189 , G06F9/325 , G06F9/3889
摘要： Provided is an apparatus and method capable of processing code to which a software pipelining is not applicable, in a CGA mode. The apparatus may include a processing unit that has a very long instruction word (VLIW) mode and a coarse-grained array (CGA) mode, and an adjusting unit configured to detect a target region to which software pipelining is not applicable, in code to be executed by the processing unit. The adjusting unit may selectively map the detected target region to one of the VLIW mode and the CGA mode according to a schedule length of the detected target region.
摘要翻译：提供了一种能够以CGA模式处理软件流水线不适用的代码的装置和方法。该装置可以包括处理单元，其具有非常长的指令字（VLIW）模式和粗粒度阵列（CGA）模式，以及调整单元，被配置为检测软件流水线不适用的目标区域，由处理单元执行。调整单元可以根据检测到的目标区域的调度长度，将检测到的目标区域选择性地映射到VLIW模式和CGA模式之一。

4. 发明申请

US20110231627A1 MEMORY MANAGING APPARATUS AND METHOD 有权
标题翻译：存储器管理装置和方法
公开(公告)号：US20110231627A1
公开(公告)日：2011-09-22
申请号：US12917173
申请日：2010-11-01
申请人： Bernhard EGGER , Tai-Song Jin , Dong-Hoon Yoo , Won-Sub Kim , Sun-Hwa Kim , Hee-Jin Ahn
发明人： Bernhard EGGER , Tai-Song Jin , Dong-Hoon Yoo , Won-Sub Kim , Sun-Hwa Kim , Hee-Jin Ahn
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0253
摘要： A memory managing apparatus and method are provided. The memory managing apparatus may determine, based on a pointer indicator bit, the target memory area on which garbage collection is to be performed, and may perform the garbage collection on the target memory area. The memory managing apparatus may generate the pointer indicator bit and store the generated pointer indicator bit in a pointer field.
摘要翻译：提供了一种存储器管理装置和方法。存储器管理装置可以基于指针指示符位来确定要在其上执行垃圾收集的目标存储器区域，并且可以在目标存储器区域上执行垃圾收集。存储器管理装置可以生成指针指示符位，并将生成的指针指示符位存储在指针字段中。

5. 发明申请

US20110225399A1 PROCESSOR AND METHOD FOR SUPPORTING MULTIPLE INPUT MULTIPLE OUTPUT OPERATION 审中-公开
标题翻译：用于支持多输入多输出操作的处理器和方法
公开(公告)号：US20110225399A1
公开(公告)日：2011-09-15
申请号：US12964377
申请日：2010-12-09
申请人： Tai-Song JIN , Dong-Hoon Yoo , Bernhard Egger , Won-Sub Kim
发明人： Tai-Song JIN , Dong-Hoon Yoo , Bernhard Egger , Won-Sub Kim
IPC分类号： G06F9/30
CPC分类号： G06F9/30065 , G06F9/3001 , G06F9/3893
摘要： A processor for supporting a MIMO operation and method of processing a MIMO instruction are provided. The MIMO operation supporting processor may include a scheduler and at least one functional unit. The scheduler may map multiple inputs of the MIMO instruction to a plurality of sequential input cycles, respectively, and may map multiple outputs of the MIMO instruction to a plurality of sequential output cycles, respectively. The output cycles may be followed by the input cycles and a predetermined number of cycles for a MIMO operation. A functional unit may read a register during sequential input cycles, may perform a MIMO operation during a predetermined number of execution cycles, and may write the result of the MIMO operation into a register during sequential output cycles.
摘要翻译：提供了一种用于支持MIMO操作的处理器和处理MIMO指令的方法。 MIMO操作支持处理器可以包括调度器和至少一个功能单元。调度器可以将MIMO指令的多个输入分别映射到多个顺序输入周期，并且可以将MIMO指令的多个输出分别映射到多个顺序输出周期。输出周期之后可以是用于MIMO操作的输入周期和预定数量的周期。功能单元可以在顺序输入周期期间读取寄存器，可以在预定数量的执行周期内执行MIMO操作，并且可以在顺序输出周期期间将MIMO操作的结果写入寄存器。

6. 发明申请

US20100088536A1 PROCESSOR AND METHOD OF DECOMPRESSING INSTRUCTION BUNDLE 有权
标题翻译：处理器和解码指令集的方法
公开(公告)号：US20100088536A1
公开(公告)日：2010-04-08
申请号：US12467536
申请日：2009-05-18
申请人： Sang-suk LEE , Tai-song Jin
发明人： Sang-suk LEE , Tai-song Jin
IPC分类号： G06F9/312 , G06F1/04
CPC分类号： G06F9/3885 , G06F9/321 , G06F9/3802 , G06F9/3853
摘要： The description relates to an instruction fetch technology of a processor that processes a plurality of instructions in parallel. The processor exploits the use of a compression code fetched during a previous clock cycle when fetching compressed instructions from a program memory and creating an instruction bundle consisting of a sequence of instructions to be processed in parallel. A compression buffer is interposed between the program memory and an instruction decompression unit, such that a compression code read in a previous clock cycle is ready at the beginning of a decompression cycle of the subsequent instruction bundle thereby avoiding a delay due to memory read latency.
摘要翻译：该描述涉及并行处理多个指令的处理器的指令获取技术。当从程序存储器中取出压缩指令并创建由要并行处理的指令序列组成的指令包时，处理器利用在先前时钟周期期间获取的压缩代码的使用。在程序存储器和指令解压缩单元之间插入压缩缓冲器，使得在随后的指令包的解压缩循环开始时，先前时钟周期中读取的压缩代码就绪，从而避免了由于存储器读取延迟引起的延迟。

7. 发明授权

US08954946B2 Static branch prediction method and code execution method for pipeline processor, and code compiling method for static branch prediction 有权
标题翻译：流水线处理器的静态分支预测方法和代码执行方法，静态分支预测的代码编译方法
公开(公告)号：US08954946B2
公开(公告)日：2015-02-10
申请号：US12692735
申请日：2010-01-25
申请人： Tai-song Jin , Dong-kwan Suh , Suk-jin Kim
发明人： Tai-song Jin , Dong-kwan Suh , Suk-jin Kim
IPC分类号： G06F9/45 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30058 , G06F9/3846
摘要： A static branch prediction method and code execution method for a pipeline processor, and a code compiling method for static branch prediction, are provided herein. The static branch prediction method includes predicting a conditional branch code as taken or not-taken, adding the prediction information, converting the conditional branch code into a jump target address setting (JTS) code including target address information, branch time information, and a test code, and scheduling codes in a block. The code may be scheduled into a last slot of the block, and the JTS code may be scheduled into an empty slot after all the other codes in the block are scheduled. When the conditional branch code is predicted as taken in the prediction operation, a target address indicated by the target address information may be fetched at a cycle time indicated by the branch time information.
摘要翻译：本文提供了一种用于流水线处理器的静态分支预测方法和代码执行方法，以及用于静态分支预测的代码编译方法。静态分支预测方法包括：预测采取或不采用的条件分支代码，将预测信息相加，将条件分支代码转换成包括目标地址信息，分支时间信息和测试的跳转目标地址设置（JTS）代码代码和调度代码。可以将代码调度到块的最后一个时隙中，并且在块中的所有其他代码被调度之后，可以将JTS代码调度到空时隙。当在预测操作中预测条件分支代码时，可以在由分支时间信息指示的周期时间获取由目标地址信息指示的目标地址。

8. 发明授权

US08856596B2 Debugging apparatus and method 有权
标题翻译：调试装置和方法
公开(公告)号：US08856596B2
公开(公告)日：2014-10-07
申请号：US13079275
申请日：2011-04-04
申请人： Jin-Seok Lee , Bernhard Egger , Dong-Hoon Yoo , Tai-Song Jin
发明人： Jin-Seok Lee , Bernhard Egger , Dong-Hoon Yoo , Tai-Song Jin
IPC分类号： G06F11/00 , G06F9/30 , G06F11/36
CPC分类号： G06F9/30076 , G06F11/3644
摘要： A debugging apparatus and method are provided. The debugging apparatus may include a breakpoint setting unit configured to store a first instruction corresponding to a breakpoint in a table, stop a program currently being executed, and insert a breakpoint instruction including current location information of the first instruction into the breakpoint; and an instruction execution unit configured to selectively execute one of the breakpoint instruction and the first instruction according to a value of a status bit.
摘要翻译：提供了一种调试装置和方法。调试装置可以包括：断点设定单元，被配置为将与断点对应的第一指令存储在表中，停止当前正在执行的程序，并将包括第一指令的当前位置信息的断点指令插入断点; 以及指令执行单元，被配置为根据状态位的值有选择地执行断点指令和第一指令之一。

9. 发明授权

US08555005B2 Memory managing apparatus and method using a pointer indicator bit to perform garbage collection 有权
标题翻译：使用指针指示符位执行垃圾回收的存储器管理装置和方法
公开(公告)号：US08555005B2
公开(公告)日：2013-10-08
申请号：US12917173
申请日：2010-11-01
申请人： Bernhard Egger , Tai-Song Jin , Dong-Hoon Yoo , Won-Sub Kim , Sun-Hwa Kim , Hee-Jin Ahn
发明人： Bernhard Egger , Tai-Song Jin , Dong-Hoon Yoo , Won-Sub Kim , Sun-Hwa Kim , Hee-Jin Ahn
IPC分类号： G06F12/00
CPC分类号： G06F12/0253
摘要： A memory managing apparatus and method are provided. The memory managing apparatus may determine, based on a pointer indicator bit, the target memory area on which garbage collection is to be performed, and may perform the garbage collection on the target memory area. The memory managing apparatus may generate the pointer indicator bit and store the generated pointer indicator bit in a pointer field.
摘要翻译：提供了一种存储器管理装置和方法。存储器管理装置可以基于指针指示符位来确定要在其上执行垃圾收集的目标存储器区域，并且可以在目标存储器区域上执行垃圾收集。存储器管理装置可以生成指针指示符位，并将生成的指针指示符位存储在指针字段中。

10. 发明申请

US20130238877A1 CORE SYSTEM FOR PROCESSING AN INTERRUPT AND METHOD FOR TRANSMISSION OF VECTOR REGISTER FILE DATA THEREFOR 审中-公开
标题翻译：用于处理中断的核心系统和用于传输矢量寄存器文件数据的方法
公开(公告)号：US20130238877A1
公开(公告)日：2013-09-12
申请号：US13672756
申请日：2012-11-09
申请人： Jin-Seok Lee , Dong-Hoon Yoo , Won-Sub Kim , Tai-Song Jin , Hae-Woo Park , Min-Wook Ahn , Hee-Jin Ahn
发明人： Jin-Seok Lee , Dong-Hoon Yoo , Won-Sub Kim , Tai-Song Jin , Hae-Woo Park , Min-Wook Ahn , Hee-Jin Ahn
IPC分类号： G06F15/76
CPC分类号： G06F9/5016 , G06F9/461
摘要： Provided is a technique for improving the transfer latency of vector register file data when an interrupt is generated. According to an aspect, when interrupt occurs, a core determines whether to store vector register file data currently being executed in a first memory or in a second memory based on whether or not the first memory can store the vector register file data therein. In response to not being able to store the vector register file data in the first memory, a data transfer unit, which is implemented as hardware, is provided to store vector register file data in the second memory.
摘要翻译：提供了一种用于在产生中断时改善向量寄存器文件数据的传送等待时间的技术。根据一方面，当中断发生时，核心基于第一存储器是否可以在其中存储向量寄存器文件数据来确定是否将当前正在执行的向量寄存器文件数据存储在第一存储器或第二存储器中。响应于不能将向量寄存器文件数据存储在第一存储器中，提供实现为硬件的数据传送单元，以将向量寄存器文件数据存储在第二存储器中。

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