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    • 1. 发明授权
    • Semiconductor device
    • 半导体器件
    • US07667244B2
    • 2010-02-23
    • US12149567
    • 2008-05-05
    • Tadashi Narita
    • Tadashi Narita
    • H01L27/10
    • H01L21/823828H01L21/823871H01L27/0207
    • On a semiconductor substrate, a gate electrode is disposed obliquely across the boundary between an N-type region and a P-type region, and thereby an effective gate width of a region, in which the boundary between the N-type region and the P-type region intersects with the gate electrode, is wider than that of the gate electrode. Accordingly, the occurrence of abnormal resistance, which makes it difficult for an electric current to flow in the gate electrode on the boundary between the N-type region and the P-type region, may be effectively suppressed without physically widening the gate width. Moreover, widening of the gate width of the gate electrode may be eliminated in suppressing the occurrence of abnormal resistance and it is not necessary to enlarge the areas of the N-type region and the P-type region, thereby inevitable enlargement of the overall size of the semiconductor device being avoided.
    • 在半导体衬底上,栅电极倾斜地设置在N型区域和P型区域之间的边界上,由此,N型区域和P型区域之间的边界的有效栅极宽度 型区域与栅电极相交,比栅电极宽。 因此,可以有效地抑制在N型区域和P型区域之间的边界上的电极中难以流入电流的异常电阻的发生,而不会使栅极宽度变宽。 此外,为了抑制异常电阻的发生,可以消除栅电极的栅极宽度的扩大,不需要扩大N型区域和P型区域的面积,不可能扩大整体尺寸 的半导体器件。
    • 3. 发明申请
    • Semiconductor device
    • 半导体器件
    • US20080303100A1
    • 2008-12-11
    • US12149567
    • 2008-05-05
    • Tadashi Narita
    • Tadashi Narita
    • H01L27/092
    • H01L21/823828H01L21/823871H01L27/0207
    • On a semiconductor substrate, a gate electrode is disposed obliquely across the boundary between an N-type region and a P-type region, and thereby an effective gate width of a region, in which the boundary between the N-type region and the P-type region intersects with the gate electrode, is wider than that of the gate electrode. Accordingly, the occurrence of abnormal resistance, which makes it difficult for an electric current to flow in the gate electrode on the boundary between the N-type region and the P-type region, may be effectively suppressed without physically widening the gate width. Moreover, widening of the gate width of the gate electrode may be eliminated in suppressing the occurrence of abnormal resistance and it is not necessary to enlarge the areas of the N-type region and the P-type region, thereby inevitable enlargement of the overall size of the semiconductor device being avoided.
    • 在半导体衬底上,栅电极倾斜地设置在N型区域和P型区域之间的边界上,由此,N型区域和P型区域之间的边界的有效栅极宽度 型区域与栅电极相交,比栅电极宽。 因此,可以有效地抑制在N型区域和P型区域之间的边界上的电极中难以流入电流的异常电阻的发生,而不会使栅极宽度变宽。 此外,为了抑制异常电阻的发生,可以消除栅电极的栅极宽度的扩大,不需要扩大N型区域和P型区域的面积,不可能扩大整体尺寸 的半导体器件。
    • 6. 发明授权
    • Method for manufacturing semiconductor device
    • 制造半导体器件的方法
    • US07629223B2
    • 2009-12-08
    • US12292511
    • 2008-11-20
    • Tadashi NaritaKatsuo Oshima
    • Tadashi NaritaKatsuo Oshima
    • H01L21/76
    • H01L21/76224H01L21/823481Y10S438/975
    • A method for manufacturing a semiconductor device includes forming a plurality of trenches for element isolation and a plurality of trenches for alignment mark on a substrate. The substrate has an active region. The method also includes laminating an oxide film on the substrate and over both of the trenches. The method also includes etching the oxide film using a resist mask that masks the element isolation trenches, so that the oxide film laminated in the active region and the oxide film laminated in the alignment mark trenches are removed. The method also includes polishing a surface of the substrate to planarize or smooth the surface of the substrate. Accordingly, those portions of the oxide film which project from the substrate surface are eliminated and the oxide film remains only inside the element isolation trenches. This divides the active region into a plurality of individual active regions for the respective semiconductor elements. The method also includes positioning the resist mask using the alignment mark trenches. The resist mask is used to fabricate the semiconductor elements in the active regions of the substrate.
    • 一种制造半导体器件的方法包括:在衬底上形成用于元件隔离的多个沟槽和用于对准标记的多个沟槽。 衬底具有活性区域。 该方法还包括在衬底上和两个沟槽上层叠氧化膜。 该方法还包括使用掩模元件隔离沟槽的抗蚀剂掩模来蚀刻氧化膜,从而去除叠层在有源区中的氧化膜和层叠在对准标记沟槽中的氧化膜。 该方法还包括抛光衬底的表面以平坦化或平滑衬底的表面。 因此,从衬底表面突出的氧化膜的那些部分被去除,并且氧化物膜仅保留在元件隔离沟槽内部。 这将有源区域划分成用于各个半导体元件的多个单独的有源区域。 该方法还包括使用对准标记沟槽定位抗蚀剂掩模。 抗蚀剂掩模用于在衬底的有源区域中制造半导体元件。