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1. 发明申请

WO2005038869A3 ELECTRONICALLY PROGRAMMABLE ANTIFUSE AND CIRCUITS MADE THEREWITH 审中-公开
标题翻译：电子可编程抗体和电路
公开(公告)号：WO2005038869A3
公开(公告)日：2006-02-09
申请号：PCT/US2004032581
申请日：2004-10-04
申请人： IBM , ABADEER WAGDI W , FIFIELD JOHN A , TONTI WILLIAM R
发明人： ABADEER WAGDI W , FIFIELD JOHN A , TONTI WILLIAM R
IPC分类号： H01L23/525 , H01L27/12 , H01L21/82 , H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit.
摘要翻译：一种反熔丝装置（120），其包括彼此串联布置的偏置元件（124）和可编程反熔丝元件（128），以形成具有位于偏置和反熔丝元件之间的输出节点（F）的分压器。当反熔丝装置处于其未编程状态时，偏置元件和反熔丝元件中的每一个都是不导电的。当反熔丝装置处于其编程状态时，偏置元件保持不导电，但是反熔丝元件是导电的。反熔丝元件在其未编程状态和编程状态之间的电阻差异导致当在反熔断器件上施加1V的电压时，在输出节点处看到的电压差为几百微升。该电压差非常高，可以使用简单的感测电路容易地感测。

2. 发明申请

WO2004100271A1 PROGRAMMABLE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：可编程半导体器件
公开(公告)号：WO2004100271A1
公开(公告)日：2004-11-18
申请号：PCT/US2003/013392
申请日：2003-04-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , TONTI, William, R. , BERRY, Wayne, S. , FIFIELD, John, A. , GUTHRIE, William, H. , KONTRA, Richard, S.
发明人： TONTI, William, R. , BERRY, Wayne, S. , FIFIELD, John, A. , GUTHRIE, William, H. , KONTRA, Richard, S.
IPC分类号： H01L29/00
CPC分类号： G11C17/16 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A programmable device includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface (S); the first end (12a) is substantially wider than the second end (12b), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current (I) flowable through the semiconductor material and the metallic material.
摘要翻译：可编程器件包括衬底（10）; 绝缘体（13）; 绝缘体上的细长半导体材料（12），具有第一和第二端的细长半导体材料和上表面（S）; 第一端部（12a）比第二端部（12b）大得多，金属材料设置在上表面上; 所述金属材料可响应于可流过所述半导体材料和所述金属材料的电流（I）沿所述上表面物理迁移。

3. 发明申请

WO2008025676A1 INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS AND FORMATION METHODS THEREFOR 审中-公开
标题翻译：集成电路的互连结构及其形成方法
公开(公告)号：WO2008025676A1
公开(公告)日：2008-03-06
申请号：PCT/EP2007/058436
申请日：2007-08-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , HSU, Louis, Lu-Chen , MANDELMAN, Jack, Allan , TONTI, William, Robert , YANG, Chih-Chao
发明人： HSU, Louis, Lu-Chen , MANDELMAN, Jack, Allan , TONTI, William, Robert , YANG, Chih-Chao
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/76814 , H01L21/76844 , H01L21/76846 , H01L21/76868 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures that include a conformal liner repair layer bridging breaches in a liner formed on roughened dielectric material in an insulating layer and methods of forming such interconnect structures. The conformal liner repair layer is formed of a conductive material, such as a cobalt-containing material. The conformal liner repair layer may be particularly useful for repairing discontinuities in a conductive liner disposed on roughened dielectric material bordering the trenches and vias of damascene interconnect structures.
摘要翻译：互连结构包括在绝缘层中形成在粗糙化介电材料上的衬垫中桥接破裂的共形衬里修复层以及形成这种互连结构的方法。保形衬里修复层由诸如含钴材料的导电材料形成。保形衬里修复层可能特别适用于修复布置在与镶嵌互连结构的沟槽和通孔相邻的粗糙化介电材料上的导电衬垫中的不连续性。

4. 发明申请

WO2009003895A1 INTEGRATED FIN-LOCAL INTERCONNECT STRUCTURE 审中-公开
标题翻译：集成式FIN局部互连结构
公开(公告)号：WO2009003895A1
公开(公告)日：2009-01-08
申请号：PCT/EP2008/058092
申请日：2008-06-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , CHENG, Kangguo , HSU, Louis, Lu-Chen , MANDELMAN, Jack, Allan , TONTI, William, Robert
发明人： CHENG, Kangguo , HSU, Louis, Lu-Chen , MANDELMAN, Jack, Allan , TONTI, William, Robert
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/785 , H01L2029/7858 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention generally relate to semiconductor devices, and more specifically to interconnecting semiconductor devices. A suicide layer may be formed on selective areas of a fin structure connecting one or more semiconductor devices or semiconductor device components. By providing suicided fin structures to locally interconnect semiconductor devices, the use of metal contacts and metal layers may be obviated, thereby allowing formation of smaller, less complex circuits.
摘要翻译：本发明的实施例一般涉及半导体器件，更具体地涉及互连半导体器件。可以在连接一个或多个半导体器件或半导体器件部件的翅片结构的选择性区域上形成硅化物层。通过提供用于局部互连半导体器件的硅芯片结构，可以避免使用金属触点和金属层，从而允许形成较小的，较不复杂的电路。

5. 发明申请

WO2008128897A3 HYBRID SUBSTRATES AND METHODS FOR FORMING SUCH HYBRID SUBSTRATES 审中-公开
公开(公告)号：WO2008128897A3
公开(公告)日：2008-10-30
申请号：PCT/EP2008/054306
申请日：2008-04-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , CANNON, Ethan, Harrison , FURUKAWA, Toshiharu , GAUDIELLO, John, Gerard , HAKEY, Mark, Charles , HOLMES, Steven, John , HORAK, David, Vaclav , KOBURGER III, Charles, William , MANDELMAN, Jack, Allan , TONTI, William, Robert
发明人： CANNON, Ethan, Harrison , FURUKAWA, Toshiharu , GAUDIELLO, John, Gerard , HAKEY, Mark, Charles , HOLMES, Steven, John , HORAK, David, Vaclav , KOBURGER III, Charles, William , MANDELMAN, Jack, Allan , TONTI, William, Robert
IPC分类号： H01L21/762
摘要： Hybrid substrates characterized by semiconductor islands of different crystal orientations and methods of forming such hybrid substrates. The methods involve using a SIMOX process to form an insulating layer. The insulating layer may divide the islands of at least one of the different crystal orientations into mutually aligned device and body regions. The body regions may be electrically floating relative to the device regions.

6. 发明申请

WO2010076074A1 INTERCONNECT STRUCTURE WITH IMPROVED DIELECTRIC LINE TO VIA ELECTROMIGRATION RESISTANT INTERFACIAL LAYER AND METHOD OF FABRICATING SAME 审中-公开
标题翻译：具有改进的介电线的互连结构通过电阻接触层及其制造方法
公开(公告)号：WO2010076074A1
公开(公告)日：2010-07-08
申请号：PCT/EP2009/064974
申请日：2009-11-11
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , BASKER, Veeraraghavan , TONTI, William, Robert , WONG, Keith, Kwong Hon , YANG, Chih-Chao
发明人： BASKER, Veeraraghavan , TONTI, William, Robert , WONG, Keith, Kwong Hon , YANG, Chih-Chao
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L21/76843 , H01L21/76814 , H01L21/76849 , H01L21/7685 , H01L21/76886 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures having improved electromigration resistance are provided that include a metallic interfacial layer (or metal alloy layer) (66) that is present at the bottom of a via opening. The via opening is located within a second dielectric material (52') that is located atop a first dielectric material (52) that includes a first conductive material (56) embedded therein. The metallic interfacial layer (or metal alloy layer) that is present at the bottom of the via opening is located between the underlying first conductive material embedded within the first dielectric and the second conductive material that is embedded within the second dielectric material. Methods of fabricating the improved electromigration resistance interconnect structures are also provided.
摘要翻译：提供具有改善的电迁移阻力的互连结构，其包括存在于通孔开口底部的金属界面层（或金属合金层）（66）。通孔开口位于第二介电材料（52'）内，第二电介质材料（52'）位于包括嵌入其中的第一导电材料（56）的第一介电材料（52）的顶部。存在于通孔开口底部的金属界面层（或金属合金层）位于埋在第一电介质内的下面的第一导电材料和嵌入在第二电介质材料内的第二导电材料之间。还提供了制造改进的电迁移电阻互连结构的方法。

7. 发明申请

WO2009086247A1 COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE WITH AN ELECTROPLATED METAL REPLACEMENT GATE 审中-公开
标题翻译：具有电镀金属替代门的补充金属氧化物半导体器件
公开(公告)号：WO2009086247A1
公开(公告)日：2009-07-09
申请号：PCT/US2008/087902
申请日：2008-12-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , BASKER, Veeraraghavan, S. , PARUCHURI, Vamsi , COTTE, John, M. , FURUKAWA, Toshiharu , TONTI, William , DELIGIANNI, Hariklia
发明人： BASKER, Veeraraghavan, S. , PARUCHURI, Vamsi , COTTE, John, M. , FURUKAWA, Toshiharu , TONTI, William , DELIGIANNI, Hariklia
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L29/517 , H01L29/66545
摘要： Disclosed herein are embodiments of a method of forming a complementary metal oxide semiconductor (CMOS) device that has at least one high aspect ratio gate structure with a void-free and seam- free metal gate conductor layer positioned on top of a relatively thin high-k gate dielectric layer. These method embodiments incorporate a gate replacement strategy that uses an electroplating process to fill, from the bottom upward, a high-aspect ratio gate stack opening with a metal gate conductor layer. The source of electrons for the electroplating process is a current passed directly through the back side of the substrate. This eliminates the need for a seed layer and ensures that the metal gate conductor layer will be formed without voids or seams. Furthermore, depending upon the embodiment, the electroplating process is performed under illumination to enhance electron flow to a given area (i.e., to enhance plating) or in darkness to prevent electron flow to a given area (i.e., to prevent plating).
摘要翻译：本文公开了形成互补金属氧化物半导体（CMOS）器件的方法的实施例，该器件具有至少一个高纵横比栅极结构，其中空隙无缝和无缝的金属栅极导体层位于相对较薄的高度 k栅介质层。这些方法实施例包括栅极替换策略，其使用电镀工艺从底部向上填充具有金属栅极导体层的高纵横比栅极堆叠开口。用于电镀工艺的电子源是直接通过衬底背面的电流。这消除了对种子层的需要，并且确保金属栅导体层将形成而没有空隙或接缝。此外，根据实施例，电镀工艺在照明下进行，以增强电子流向给定区域（即，为了增强电镀）或在黑暗中以防止电子流向给定区域（即防止电镀）。

8. 发明申请

WO2007051765A2 ELECTRICALLY PROGRAMMABLE FUSE 审中-公开
标题翻译：电可编程保险丝
公开(公告)号：WO2007051765A2
公开(公告)日：2007-05-10
申请号：PCT/EP2006/067883
申请日：2006-10-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , HSU, Louis, Lu-Chen , MANDELMAN, Jack , TONTI, William
发明人： HSU, Louis, Lu-Chen , MANDELMAN, Jack , TONTI, William
IPC分类号： H01L23/525
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An electrically programmable fuse (eFuse) includes (1) a semiconducting layer above an insulating oxide layer of a substrate; (2) a diode formed in the semiconducting layer; and (3) a silicide layer formed on the diode. The diode comprises an N+,p-,P+ or P+,n-,N+ structure.
摘要翻译：电可编程熔丝（eFuse）包括（1）衬底绝缘氧化物层之上的半导体层; （2）形成在半导体层中的二极管; 和（3）二极管上形成的硅化物层。二极管包括N +，p-，P +或P +，n-，N +结构。

9. 发明申请

WO2005038869A2 ELECTRONICALLY PROGRAMMABLE ANTIFUSE AND CIRCUITS MADE THEREWITH 审中-公开
标题翻译：电子可编程抗体和电路
公开(公告)号：WO2005038869A2
公开(公告)日：2005-04-28
申请号：PCT/US2004/032581
申请日：2004-10-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ABADEER, Wagdi, W. , FIFIELD, John, A. , TONTI, William, R.
发明人： ABADEER, Wagdi, W. , FIFIELD, John, A. , TONTI, William, R.
IPC分类号： H01L
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit.
摘要翻译：一种反熔丝装置（120），其包括彼此串联布置的偏置元件（124）和可编程反熔丝元件（128），以形成具有位于偏置和反熔丝元件之间的输出节点（F）的分压器。当反熔丝装置处于其未编程状态时，偏置元件和反熔丝元件中的每一个都是不导电的。当反熔丝装置处于其编程状态时，偏置元件保持不导电，但是反熔丝元件是导电的。反熔丝元件在其未编程状态和编程状态之间的电阻差异导致当在反熔断器件上施加1V的电压时，在输出节点处看到的电压差为几百微升。该电压差非常高，可以使用简单的感测电路容易地感测。

10. 发明申请

WO2004059726A1 INTEGRATED ANTIFUSE STRUCTURE FOR FINFET AND CMOS DEVICES 审中-公开
标题翻译： FINFET和CMOS器件的集成抗结构
公开(公告)号：WO2004059726A1
公开(公告)日：2004-07-15
申请号：PCT/US2002/041182
申请日：2002-12-20
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , RANKIN, Jed, H. , ABADEER, Wagdi, W. , BROWN, Jeffrey, S. , CHATTY, Kiran, V. , TONTI, William, R. , GAUTHIER, Robert, J., Jr. , FRIED, David, M.
发明人： RANKIN, Jed, H. , ABADEER, Wagdi, W. , BROWN, Jeffrey, S. , CHATTY, Kiran, V. , TONTI, William, R. , GAUTHIER, Robert, J., Jr. , FRIED, David, M.
IPC分类号： H01L21/82
CPC分类号： H01L21/84 , H01L23/5252 , H01L27/0629 , H01L27/11807 , H01L27/1203 , H01L29/785 , H01L29/7854 , H01L2924/0002 , H01L2924/00
摘要： A method is described for fabricating and antifuse structure (100) integrated with a semiconductor device such as a FINFET or planar CMOS devise. A region of semiconducting material (11) is provided overlying an insulator (3) disposed on a substrate (10); an etching process exposes a plurality of corners (111-114) in the semiconducting material. The exposed corners are oxidized to form elongated tips (111t-114t) at the corners; the oxide (31) overlying the tips is removed. An oxide layer (51), such as a gate oxide, is then formed on the semiconducting material and overlying the corners; this layer has a reduced thickness at the corners. A layer of conducting material (60) is formed in contact with the oxide layer (51) at the corners, thereby forming a plurality of possible breakdown paths between the semiconducting material and the layer of conducting material through the oxide layer. Applying a voltage, such as a burn-in voltage, to the structure converts at least one of the breakdown paths to a conducting path (103, 280).
摘要翻译：描述了与半导体器件（例如FINFET或平面CMOS器件）集成的制造和反熔丝结构（100）的方法。设置在设置在基板（10）上的绝缘体（3）上的半导体材料（11）的区域; 蚀刻工艺暴露了半导体材料中的多个拐角（111-114）。暴露的拐角被氧化，在角落处形成细长的尖端（111t-114t）去除顶部上方的氧化物（31）。然后在半导体材料上形成氧化物层（例如栅极氧化物），并覆盖在角部上; 该层在拐角处具有减小的厚度。在角部处形成与氧化物层（51）接触的导电材料层（60），从而通过氧化物层在半导体材料和导电材料层之间形成多个可能的击穿路径。将诸如老化电压的电压施加到结构将至少一个击穿路径转换成导电路径（103,280）。

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