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    • 2. 发明申请
    • SEMICONDUCTEUR CHIP AND RETICLE FOR MANUFACTURING SEMICONDUCTOR
    • 制造半导体的半导体芯片及其制造方法
    • WO1997050111A1
    • 1997-12-31
    • PCT/JP1997002196
    • 1997-06-25
    • HITACHI, LTD.TAKAGI, YujiMATSUYAMA, YukioHIROI, TakashiWATANABE, MasahiroTANAKA, MakiISHIKAWA, SeijiSUGIMOTO, Aritoshi
    • HITACHI, LTD.
    • H01L21/02
    • G03F9/70H01L23/544H01L2223/54413H01L2223/54433H01L2223/54453H01L2223/54473H01L2924/0002H01L2924/00
    • An alignment marker used for another use, such as in a stepper, has been conventionally used for finding the position, specified by CAD data, of a final functional defect of a semiconductor chip detected by fail bit inspections. However, this alignment marker does not coincide exactly with a design coordinate system which is established on the basis of a virtually existing scribe center and, when the semiconductor chip is positioned by using the marker, an error of tens of micrometers occurs. Therefore, at the time of observing a defect at a point designated by design coordinate values, a considerable amount of man-hour has been required, because the designated point of the defect to be observed is deviated from the actual position by about several to ten cells and the vicinity of the point must be visually searched for the defect. According to this invention, patterns such that the position on each coordinate axis of the design coordinate axis is encoded so that the position in the chip formed on a semiconductor wafer can be recognized from design coordinate values are provided in horizontal and vertical specific areas of the uppermost layer at the time of visual observation or of a layer which is detectable at the time of observation by utilizing the peripheral region of the chip. The patterns are inputted into a computer at the time of observation, positional information on each coordinate axis is read out by decoding the encoded pattern, and the chip is positioned.
    • 通常使用用于另一种用途的对准标记,例如在步进机中,用于找出由CAD数据指定的通过故障位检查检测到的半导体芯片的最终功能缺陷的位置。 然而,该对准标记与基于实际存在的刻划中心建立的设计坐标系不完全一致,并且当通过使用标记定位半导体芯片时,出现数十微米的误差。 因此,在由设计坐标值指定的点观察缺陷时,需要相当多的工时,因为要观察的缺陷的指定点偏离实际位置大约几十个 细胞和点的附近必须在视觉上搜索缺陷。 根据本发明,在设计坐标轴的每个坐标轴上的位置被编码使得能够从设计坐标值识别形成在半导体晶片上的芯片中的位置的图案被提供在水平和垂直的特定区域中 在目视观察时的最上层,或通过利用芯片的周边区域在观察时可检测的层。 在观察时将图案输入到计算机中,通过对编码图案进行解码来读出各坐标轴上的位置信息,并对芯片进行定位。
    • 4. 发明申请
    • TWO-DIMENSIONAL ENCODER, HOLOGRAPHIC MEMORY DEVICE AND HOLOGRAPHIC MEMORY MEDIUM
    • 二维编码器,全息记忆装置和全息记忆媒体
    • WO2008044718A1
    • 2008-04-17
    • PCT/JP2007/069792
    • 2007-10-03
    • MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.TAKAGI, YujiUSUI, MakotoKASAZUMI, Kenichi
    • TAKAGI, YujiUSUI, MakotoKASAZUMI, Kenichi
    • G11B7/0065G03H1/16G11B20/00G11C13/04
    • G11B7/0065G03H1/16G11B20/12G11C13/045
    • A two-dimensional encoder stores data on a holographic memory. The encoder encodes data of k bits (where k is an integer and k ≥ 3) into n pixels arranged two-dimensionally (where n is an integer and n ≥ 6). The encoder includes a first processing section 31 for classifying the n pixels into first and second groups of subblocks 11 and 12 using k1 bits out of the data of k bits (where k1 is an integer and k1 ≥ 1). Each of the subblocks 11 in the first group consists of m pixels (where m is an integer and m ≥ 2), and the number of the subblocks 11 forming the first group is s1 (where s1 is an integer and s1 ≥ 2). Each of the subblocks 12 in the second group also consists of m pixels, and the number of the subblocks 12 forming the second group is s2 (where s2 is an integer and s2 ≥ 1). The encoder further includes a second processing section 32 for turning ON p pixels (where p is an integer and 1 ≤ p ≤ m/2) out of the m pixels forming each subblock 11 in the first group and turning OFF all of the m pixels forming each subblock 12 in the second group using the other k2 bits of the data of k bits (where k2=k-k1).
    • 二维编码器将数据存储在全息存储器上。 编码器将k位(其中k是整数,k = 3)的数据编码成二维布置的n个像素(其中n是整数,n = 6)。 编码器包括第一处理部分31,用于使用k位数据(其中k1是整数和k1 = 1)中的k1位将n个像素分类为第一和第二子块11和12组。 第一组中的每个子块11由m个像素(其中m是整数,m = 2)组成,并且形成第一组的子块11的数量是s1(其中s1是整数,s1 = 2)。 第二组中的每个子块12也由m个像素组成,并且形成第二组的子块12的数量是s2(其中s2是整数,s2 = 1)。 编码器还包括用于在形成第一组中的每个子块11的m个像素中打开p个像素(其中p是整数并且1 = p = m / 2)的第二处理部分32,并且关闭所有m个像素 使用k位数据的其他k2位(其中k2 = k-k1)来形成第二组中的每个子块12。
    • 10. 发明授权
    • Data recording/reproducing apparatus having plural optical disk drives
operating in parallel
    • 数据记录/重放装置具有并行操作的多个光盘驱动器
    • US5243581A
    • 1993-09-07
    • US556330
    • 1990-07-23
    • Takagi YujiIsao SatohYoshihisa FukushimaYasushi AzumataniHiroshi Hamasaka
    • Takagi YujiIsao SatohYoshihisa FukushimaYasushi AzumataniHiroshi Hamasaka
    • G06F3/06G11B19/20G11B19/28G11B20/10G11B27/00G11B27/10
    • G11B19/20G06F3/0601G11B19/28G11B20/10G11B27/002G11B27/10G06F2003/0692G11B2020/10916G11B2220/20
    • An optical disk recording and/or reproducing apparatus realizes a high ability to transmit data by operating a plurality of optical disk drives in parallel. By actuating the data recording or reproducing operation in parallel after these optical disk drives all have completed seeking the target track, deviation in synchronism between these drives can be suppressed below a one track maximum, resulting in the parallel operation of a plurality of optical disk drives using a a small capacity memory. In addition, by transmitting data via a high speed FIFO memory connected to each drive interface and a host interface to a RAM, speedy data transmission using the parallel operation of the plurality of drives is made possible. Further, a plurality of dual port control circuits each successively switches an access to each of a plurality of RAMs to a data transmission from or to a host computer and a data transmission from or to each drive, and the data transmission is executed between one of the RAMs and the host computer and at the same time, the data transmission is executed between each of the RAMs and each drive, thus being capable of transmitting data rapidly using the parallel operation of the plurality of drives.
    • 光盘记录和/或再现装置通过并行操作多个光盘驱动器来实现高数据传输数据的能力。 通过在这些光盘驱动器都完成寻找目标轨道之后并行地启动数据记录或再现操作,可以将这些驱动器之间的同步偏差抑制到低于一个磁道最大值,导致多个光盘驱动器的并行操作 使用一个小容量的内存。 此外,通过经由连接到每个驱动接口的高速FIFO存储器和主机接口向RAM发送数据,使得能够使用多个驱动器的并行操作的快速数据传输成为可能。 此外,多个双端口控制电路各自依次将对多个RAM中的每一个的访问切换到来自主计算机的数据传输或来自主计算机的数据传输,以及来自或来自每个驱动器的数据传输,并且数据传输在 RAM和主计算机,并且同时在每个RAM和每个驱动器之间执行数据传输,从而能够使用多个驱动器的并行操作快速地发送数据。