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1. 发明申请

US20080149936A1 PROCESS FOR INTEGRATNG A III-N TYPE COMPONENT ON A (001) NOMINAL SILICIUM SUBSTRATE 有权
标题翻译：在（001）名称硅基底上形成III-N型组分的方法
公开(公告)号：US20080149936A1
公开(公告)日：2008-06-26
申请号：US11941590
申请日：2007-11-16
申请人： SYLVAIN JOBLOT , Fabrice Semond , Jean Massies , Yvon Cordier , Jean-Yves Duboz
发明人： SYLVAIN JOBLOT , Fabrice Semond , Jean Massies , Yvon Cordier , Jean-Yves Duboz
IPC分类号： H01L21/763 , H01L31/0368
CPC分类号： H01L21/02658 , C30B23/025 , C30B23/04 , C30B25/04 , C30B25/183 , C30B29/406 , H01L21/02381 , H01L21/02458 , H01L21/0254 , H01L21/02639 , H01L21/02664 , H01L27/0605 , H01L29/2003 , H01L33/007
摘要： A process is provided for integrating a III-N component, such as GaN, on a (001) or (100) nominal silicon substrate. There are arranged a texture of elementary areas each comprising an individual surface, with the texture comprising at least one hosting area intended to receive a III-N component. A mask layer is deposited on non-hosting areas which are not intended to receive a III-N type component. The hosting area is locally prepared so as to generate on the surface of the area one domain comprising one single type of terrace. There is grown by Molecular Beam Epitaxy or Metalorganic Vapor Phase Epitaxy on the hosting area one intermediary AlN buffer layer, followed by the growth of one III-N based material so as to realize a substantially monocrystalline structure. There is eliminated the mask layer located on non-hosting areas as well as surface polycrystalline layers deposited above the mask layers, and MOS/CMOS structures are subsequent integrated on at least some of the non-hosting areas.
摘要翻译：提供了在（001）或（100）标称硅衬底上将诸如GaN的III-N成分整合的工艺。布置了各自包括单独表面的基本区域的纹理，其中纹理包括用于接收III-N分量的至少一个托管区域。掩模层沉积在不意图接收III-N型组件的非托管区域上。托管区域是本地准备的，以便在该区域的表面上生成包括一个单一类型的露台的一个域。通过分子束外延或金属有机气相外延生长在托管区域一个中间AlN缓冲层，随后生长一种III-N基材料，以实现基本上单晶结构。消除了位于非托管区域上的掩模层以及沉积在掩模层上方的表面多晶层，随后将MOS / CMOS结构集成在至少一些非托管区域上。

2. 发明授权

US08593234B2 Bragg mirror and BAW resonator with a high quality factor on the bragg mirror 有权
标题翻译：布拉格镜和布拉格镜具有高品质因数的BAW谐振器
公开(公告)号：US08593234B2
公开(公告)日：2013-11-26
申请号：US12896361
申请日：2010-10-01
申请人： Pierre Bar , Sylvain Joblot , David Petit , Jean-Francois Carpentier
发明人： Pierre Bar , Sylvain Joblot , David Petit , Jean-Francois Carpentier
IPC分类号： H03H9/15 , H03H9/05 , H03H9/54
CPC分类号： H03H3/02 , H03H9/175 , H03H2003/025
摘要： A method for manufacturing a bulk acoustic wave resonator, each resonator including: above a substrate, a piezoelectric resonator, and next to the piezoelectric resonator, a contact pad connected to an electrode of the piezoelectric resonator; and, between the piezoelectric resonator and the substrate, a Bragg mirror including at least one conductive layer extending between the pad and the substrate and at least one upper silicon oxide layer extending between the pad and the substrate, the method including the steps of: depositing the upper silicon oxide layer; and decreasing the thickness unevenness of the upper silicon oxide layer due to the deposition method, so that this layer has a same thickness to within better than 2%, and preferably to within better than 1%, at the level of each pad.
摘要翻译：一种制造体声波谐振器的方法，每个谐振器包括：在基板上方，压电谐振器上方，并且紧邻压电谐振器，连接到压电谐振器的电极的接触焊盘; 并且在所述压电谐振器和所述基板之间，布拉格反射镜包括在所述焊盘和所述衬底之间延伸的至少一个导电层和在所述焊盘和所述衬底之间延伸的至少一个上部氧化硅层，所述方法包括以下步骤：上氧化硅层; 并且由于沉积方法而减小上部氧化硅层的厚度不均匀性，使得该层在每个焊盘的水平处具有相同的厚度，优于2％以内，优选在1％以内。

3. 发明授权

US08397360B2 Method for manufacturing a monolithic oscillator with bulk acoustic wave (BAW) resonators 有权
标题翻译：用于制造具有体声波（BAW）谐振器的单片振荡器的方法
公开(公告)号：US08397360B2
公开(公告)日：2013-03-19
申请号：US12896394
申请日：2010-10-01
申请人： Pierre Bar , Sylvain Joblot , Jean-Francois Carpentier
发明人： Pierre Bar , Sylvain Joblot , Jean-Francois Carpentier
IPC分类号： H01G7/00
CPC分类号： H03H3/04 , H03H2003/0442 , Y10T29/435 , Y10T29/49002 , Y10T29/49004 , Y10T29/49005 , Y10T29/4908
摘要： A method of adjustment on manufacturing of a monolithic oscillator including circuit elements and a BAW resonator, this method including the steps of: a) forming the circuit elements and the resonator and electrically connecting them; b) covering the resonator with a frequency adjustment layer; c) measuring the output frequency of the oscillator; d) modifying the thickness of the frequency adjustment layer to modify the output frequency of the oscillator.
摘要翻译：一种调整制造包括电路元件和BAW谐振器的单片振荡器的方法，该方法包括以下步骤：a）形成电路元件和谐振器并将它们电连接; b）用频率调节层覆盖谐振器; c）测量振荡器的输出频率; d）修改频率调节层的厚度以修改振荡器的输出频率。

4. 发明授权

US08975737B2 Transmission line for electronic circuits 有权
标题翻译：电子线路传输线
公开(公告)号：US08975737B2
公开(公告)日：2015-03-10
申请号：US13279138
申请日：2011-10-21
申请人： Pierre Bar , Sylvain Joblot , Jean-François Carpentier
发明人： Pierre Bar , Sylvain Joblot , Jean-François Carpentier
IPC分类号： H01L23/02 , H01P3/08 , H01L23/66 , H01L25/065 , H01P5/02 , H01L27/00
CPC分类号： H01P3/082 , H01L23/66 , H01L25/0657 , H01L2223/6627 , H01L2225/06513 , H01L2225/06527 , H01L2924/0002 , H01P5/028 , H01L2924/00
摘要： A transmission line formed in a device including a stack of first and second chips having their front surfaces facing each other and wherein a layer of a filling material separates the front surface of the first chip from the front surface of the second chip, this line including: a conductive strip formed on the front surface side of the first chip in at least one metallization level of the first chip; and a ground plane made of a conductive material formed in at least one metallization level of the second chip.
摘要翻译：一种传输线，形成在包括第一和第二芯片堆叠的器件中，其前表面彼此面对，并且其中填充材料层将第一芯片的前表面与第二芯片的前表面分离，该线包括：形成在所述第一芯片的至少一个金属化层中的所述第一芯片的前表面侧上的导电条; 以及由在第二芯片的至少一个金属化层中形成的导电材料制成的接地平面。

5. 发明授权

US08841749B2 Semiconductor device comprising a capacitor and an electrical connection via, and fabrication method 有权
标题翻译：包括电容器和电连接通孔的半导体器件及其制造方法
公开(公告)号：US08841749B2
公开(公告)日：2014-09-23
申请号：US13298823
申请日：2011-11-17
申请人： Sylvain Joblot , Alexy Farcy , Jean-Francois Carpentier , Pierre Bar
发明人： Sylvain Joblot , Alexy Farcy , Jean-Francois Carpentier , Pierre Bar
IPC分类号： H01L21/02 , H01L23/58 , H01L49/02 , H01L23/64 , H01L23/48 , H01L21/768 , H01L23/522
CPC分类号： H01L23/481 , H01L21/76898 , H01L23/5223 , H01L23/642 , H01L28/91 , H01L2224/14181
摘要： A main blind hole is formed in a front face of a wafer having a rear face. A through capacitor is formed in the main blind hole including a conductive outer electrode, a dielectric intermediate layer, and a filling conductive material forming an inner electrode. Cylindrical portions of the outer electrode, the dielectric intermediate layer and the inner electrode have front ends situated in a plane of the front face of the wafer. A secondary rear hole is formed in the rear face of the wafer to reveal a bottom of the outer electrode. A rear electrical connection is made to contact the bottom of the outer electrode through the secondary rear hole. A through hole via filled with a conductive material is provided adjacent the through capacitor. An electrical connection is made on the rear face between the rear electrical connection and the through hole via.
摘要翻译：在具有背面的晶片的正面形成有主盲孔。在主盲孔中形成贯通电容器，其包括导电外电极，电介质中间层和形成内电极的填充导电材料。外部电极，电介质中间层和内部电极的圆柱形部分具有位于晶片正面的平面内的前端。在晶片的背面形成有副后孔以露出外电极的底部。后电气连接通过次级后孔与外部电极的底部接触。在贯通电容器附近提供填充有导电材料的通孔通孔。在后电气连接和通孔通孔之间的后表面上形成电连接。

6. 发明授权

US08756778B2 Method of adjustment during manufacture of a circuit having a capacitor 有权
标题翻译：制造具有电容器的电路时的调整方法
公开(公告)号：US08756778B2
公开(公告)日：2014-06-24
申请号：US13159244
申请日：2011-06-13
申请人： Pierre Bar , Sylvain Joblot , David Petit
发明人： Pierre Bar , Sylvain Joblot , David Petit
IPC分类号： H01G7/00
CPC分类号： H01G4/228 , H01G4/255 , H01G13/06 , H01L22/14 , H01L22/20 , H01L28/60 , H01L2924/0002 , H03H3/04 , H03H9/0542 , H03H2003/0464 , Y10T29/435 , Y10T29/49002 , Y10T29/49005 , Y10T29/49155 , Y10T29/49156 , H01L2924/00
摘要： A method of adjustment during manufacture of a capacitance of a capacitor supported by a substrate, the method including the steps of: a) forming a first electrode parallel to the surface of the substrate and covering it with a dielectric layer; b) forming, on a first portion of the dielectric layer, a second electrode; c) measuring the electrical signal between the first electrode and the second electrode, and deducing therefrom the capacitance to be added to obtain the desired capacitance; d) thinning down a second portion of the dielectric layer, which is not covered by the second electrode, so that the thickness of this second portion is adapted to the forming of the deduced capacitance; and e) forming a third electrode on the thinned-down portion and connecting it to the second electrode.
摘要翻译：一种在由衬底支撑的电容器的电容制造过程中进行调节的方法，所述方法包括以下步骤：a）形成平行于衬底表面并用介电层覆盖的第一电极; b）在电介质层的第一部分上形成第二电极; c）测量第一电极和第二电极之间的电信号，并从其中推导出待加电容以获得所需电容; d）使未被第二电极覆盖的电介质层的第二部分变薄，使得该第二部分的厚度适于形成推导的电容; 以及e）在所述减薄部分上形成第三电极并将其连接到所述第二电极。

7. 发明授权

US08587921B2 Method of adjustment on manufacturing of a circuit having a resonant element 有权
标题翻译：具有谐振元件的电路的制造调整方法
公开(公告)号：US08587921B2
公开(公告)日：2013-11-19
申请号：US12896093
申请日：2010-10-01
申请人： Pierre Bar , Sylvain Joblot , David Petit
发明人： Pierre Bar , Sylvain Joblot , David Petit
IPC分类号： H01G4/005 , H01G4/06
CPC分类号： H03H3/04 , H01G4/228 , H01G4/255 , H01G13/06 , H01L22/14 , H01L22/20 , H01L28/60 , H01L2924/0002 , Y10T29/43 , Y10T29/49004 , H01L2924/00
摘要： A method of adjustment in the manufacture of a capacitance of a capacitor supported by a substrate, the method including the steps of: a) forming a first electrode parallel to the surface of the substrate and covering it with a dielectric layer; b) forming, on a first portion of the dielectric layer, a second electrode; c) measuring the capacitance between the first electrode and the second electrode, and deducing therefrom the capacitance to be added to obtain the desired capacitance; d) thinning down a second portion of the dielectric layer, which is not covered by the second electrode, so that the thickness of this second portion is adapted to the forming of the deduced capacitance; and e) forming a third electrode on the thinned-down portion and connecting it to the second electrode.
摘要翻译：一种调整由衬底支撑的电容器的电容的制造方法，所述方法包括以下步骤：a）形成平行于衬底表面并用电介质层覆盖的第一电极; b）在所述电介质层的第一部分上形成第二电极; c）测量第一电极和第二电极之间的电容，并从其中推导出要加入的电容以获得所需电容; d）使未被第二电极覆盖的电介质层的第二部分变薄，使得该第二部分的厚度适于形成推导的电容; 以及e）在所述减薄部分上形成第三电极并将其连接到所述第二电极。

8. 发明申请

US20120320550A1 METHOD FOR ELECTRICAL CONNECTION BETWEEN ELEMENTS OF A THREE-DIMENSIONAL INTEGRATED STRUCTURE AND CORRESPONDING DEVICE 有权
标题翻译：三维集成结构元件与相应器件之间电气连接的方法
公开(公告)号：US20120320550A1
公开(公告)日：2012-12-20
申请号：US13517819
申请日：2012-06-14
申请人： Pierre Bar , Sylvain Joblot , Jean-Francois Carpentier
发明人： Pierre Bar , Sylvain Joblot , Jean-Francois Carpentier
IPC分类号： H05K1/11 , H05K3/36 , H05K3/30
CPC分类号： H01L23/49827 , H01L21/486 , H01L23/147 , H01L2924/0002 , Y10T29/4913 , Y10T29/49155 , H01L2924/00
摘要： A link device for three-dimensional integrated structure may include a module having a first end face designed to be in front of a first element of the structure, and a second end face designed to be placed in front of a second element of the structure. The two end faces may be substantially parallel, and the module including a substrate having a face substantially perpendicular to the two end faces and carrying an electrically conducting pattern formed in a metallization level on top of the face and enclosed in an insulating region. The electrically conducting pattern may include a first end part emerging onto the first end face and a second end part emerging onto the second end face and connected to the first end part.
摘要翻译：用于三维一体化结构的连杆装置可以包括具有设计成在结构的第一元件的前面的第一端面和设计成放置在结构的第二元件的前面的第二端面的模块。两个端面可以是基本上平行的，并且该模块包括具有基本上垂直于两个端面的表面的基底，并且承载形成在表面顶部的金属化水平并且封闭在绝缘区域中的导电图案。导电图案可以包括出现在第一端面上的第一端部和露出到第二端面上并连接到第一端部的第二端部。

9. 发明申请

US20120133021A1 SEMICONDUCTOR DEVICE COMPRISING A CAPACITOR AND AN ELECTRICAL CONNECTION VIA, AND FABRICATION METHOD 有权
标题翻译：包含电容器和电气连接的半导体器件，以及制造方法
公开(公告)号：US20120133021A1
公开(公告)日：2012-05-31
申请号：US13298823
申请日：2011-11-17
申请人： Sylvain Joblot , Alexy Farcy , Jean-Francois Carpentier , Pierre Bar
发明人： Sylvain Joblot , Alexy Farcy , Jean-Francois Carpentier , Pierre Bar
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L23/481 , H01L21/76898 , H01L23/5223 , H01L23/642 , H01L28/91 , H01L2224/14181
摘要： A main blind hole is formed in a front face of a wafer having a rear face. A through capacitor is formed in the main blind hole including a conductive outer electrode, a dielectric intermediate layer, and a filling conductive material forming an inner electrode. Cylindrical portions of the outer electrode, the dielectric intermediate layer and the inner electrode have front ends situated in a plane of the front face of the wafer. A secondary rear hole is formed in the rear face of the wafer to reveal a bottom of the outer electrode. A rear electrical connection is made to contact the bottom of the outer electrode through the secondary rear hole. A through hole via filled with a conductive material is provided adjacent the through capacitor. An electrical connection is made on the rear face between the rear electrical connection and the through hole via.
摘要翻译：在具有背面的晶片的正面形成有主盲孔。在主盲孔中形成贯通电容器，其包括导电外电极，电介质中间层和形成内电极的填充导电材料。外部电极，电介质中间层和内部电极的圆柱形部分具有位于晶片正面的平面内的前端。在晶片的背面形成有副后孔以露出外电极的底部。后电气连接通过次级后孔与外部电极的底部接触。在贯通电容器附近提供填充有导电材料的通孔通孔。在后电气连接和通孔通孔之间的后表面上形成电连接。

10. 发明授权

US08841748B2 Semiconductor device comprising a capacitor and an electrical connection via and fabrication method 有权
标题翻译：包括电容器和电连接通孔及其制造方法的半导体器件
公开(公告)号：US08841748B2
公开(公告)日：2014-09-23
申请号：US13298735
申请日：2011-11-17
申请人： Sylvain Joblot , Alexis Farcy , Jean-Francois Carpentier , Pierre Bar
发明人： Sylvain Joblot , Alexis Farcy , Jean-Francois Carpentier , Pierre Bar
IPC分类号： H01L21/02 , H01L23/58 , H01L21/768 , H01L23/48 , H01L23/522
CPC分类号： H01L23/5223 , H01L21/76898 , H01L23/481 , H01L2224/02372 , H01L2224/0401 , H01L2224/05548 , H01L2224/13022 , H01L2224/13024 , H01L2224/14181 , H01L2224/16145
摘要： A dielectric wafer has, on top of its front face, a front electrical connection including an electrical connection portion. A blind hole passes through from a rear face of the wafer to at least partially reveal a rear face of the electrical connection portion. A through capacitor is formed in the blind hole. The capacitor includes a first conductive layer covering the lateral wall and the electrical connection portion (forming an outer electrode), a dielectric intermediate layer covering the first conductive layer (forming a dielectric membrane), and a second conductive layer covering the dielectric intermediate layer (forming an inner electrode). A rear electrical connection is made to the inner electrode.
摘要翻译：电介质晶片在其正面的顶部具有包括电连接部分的前电连接。盲孔从晶片的后表面穿过至少部分地露出电连接部分的后表面。在盲孔中形成贯通电容器。电容器包括覆盖侧壁和电连接部分（形成外电极）的第一导电层，覆盖第一导电层（形成电介质膜）的介电中间层和覆盖电介质中间层的第二导电层形成内电极）。对内部电极进行后部电连接。

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