专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06903567B2 Test apparatus having multiple test sites at one handler and its test method 有权
公开(公告)号：US06903567B2
公开(公告)日：2005-06-07
申请号：US10672994
申请日：2003-09-25
申请人： Ae-Yong Chung , Sung-Ok Kim , Kyeong-Seon Shin , Jeong-Ho Bang
发明人： Ae-Yong Chung , Sung-Ok Kim , Kyeong-Seon Shin , Jeong-Ho Bang
IPC分类号： G01R31/26 , G01R31/01 , G01R31/28
CPC分类号： G01R31/2893 , G01R31/01 , G01R31/2851
摘要： A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus.

2. 发明授权

US06857090B2 System and method for automatically analyzing and managing loss factors in test process of semiconductor integrated circuit devices 有权
标题翻译：半导体集成电路器件测试过程中自动分析和管理损耗因子的系统和方法
公开(公告)号：US06857090B2
公开(公告)日：2005-02-15
申请号：US09971934
申请日：2001-10-09
申请人： Kyu Sung Lee , Ae Yong Chung , Sung Ok Kim
发明人： Kyu Sung Lee , Ae Yong Chung , Sung Ok Kim
IPC分类号： G01R31/26 , G01R31/28 , G06F17/00 , H03K19/03
CPC分类号： G01R31/2834 , G11C2029/5606
摘要： A system and method automatically analyzes and manages loss factor data of test processes in which a great number of IC devices are tested as a lot with a number of testers. The lot contains a predetermined number of identical IC devices, and the lot test process is performed sequentially according to a predetermined number of test cycles. The system include a means for verifying test results for each of the test cycles and for determining whether or not a re-test is to be performed and an IC device loading/unloading means for loading IC devices to be tested and contained in the lot to a test head and for unloading the tested IC devices from the test head by sorting the tested IC devices according to the test results. The system also includes raw data generating means for generating raw data on the basis of time data occurring when the test process is performed; data calculating means for calculating testing time data, index time data based on the raw data, and loss time data; data storage means for storing the raw data and the calculated data; and data analyzing and outputting means for analyzing the raw data and the calculated data according to the lots, the plurality of testers and the IC device loading/unloading means and for outputting the analyzed output through an user interface. The test system includes testers, a server system and terminal computer, and the server system is provided with data storage means for integrally manipulating time data generated by the testers according to lots and test cycles and for storing manipulated time data.
摘要翻译：系统和方法自动分析和管理测试过程的损耗因子数据，其中大量的IC器件与许多测试人员进行了很多测试。批量包含预定数量的相同的IC器件，并且批次测试过程根据预定数量的测试周期顺序地执行。该系统包括用于验证每个测试周期的测试结果以及用于确定是否要执行重新测试的装置和用于将待测试和包含在批中的IC设备加载到的IC设备加载/卸载装置测试头，并根据测试结果对测试的IC器件进行分类，从测试头卸载测试的IC器件。该系统还包括：原始数据生成装置，用于根据执行测试处理时发生的时间数据生成原始数据; 用于计算测试时间数据，基于原始数据的索引时间数据和丢失时间数据的数据计算装置; 用于存储原始数据和计算数据的数据存储装置; 以及数据分析和输出装置，用于根据批次，多个测试器和IC装置加载/卸载装置分析原始数据和计算数据，并通过用户界面输出分析的输出。测试系统包括测试器，服务器系统和终端计算机，并且服务器系统设置有数据存储装置，用于根据批次和测试周期对测试者生成的时间数据进行整体操作并存储操纵的时间数据。

3. 发明授权

US07602172B2 Test apparatus having multiple head boards at one handler and its test method 有权
标题翻译：在一个处理机上具有多个头板的测试装置及其测试方法
公开(公告)号：US07602172B2
公开(公告)日：2009-10-13
申请号：US12109299
申请日：2008-04-24
申请人： Ae-Yong Chung , Sung-Ok Kim , Kyeong-Seon Shin , Jeong-Ho Bang
发明人： Ae-Yong Chung , Sung-Ok Kim , Kyeong-Seon Shin , Jeong-Ho Bang
IPC分类号： G01R31/26
CPC分类号： G01R31/2893 , G01R31/01 , G01R31/2851
摘要： A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus.
摘要翻译：测试装置包括连接到测试器的一个处理器和分成两个或更多个站点或两个或更多个测试板的一个测试板。由于只有测试板（或测试板）上的站点需要复制，而不是处理器的加载通道或分拣机，所以测试设备可以方便地紧凑。此外，在一个站点或一个测试板上测试半导体器件时，可以根据测试结果对另一个站点中的另一个站点或另一个测试板上的半导体器件进行分类。这使得能够减少或消除测试器空闲时间以优化测试设备的效率。

4. 发明申请

US20090140761A1 METHOD OF TESTING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：测试半导体器件的方法
公开(公告)号：US20090140761A1
公开(公告)日：2009-06-04
申请号：US12255850
申请日：2008-10-22
申请人： Sung-Ok KIM , Ae-Yong CHUNG , Se-Rae CHO , Chul-Min LEE , Eun-Seok LEE
发明人： Sung-Ok KIM , Ae-Yong CHUNG , Se-Rae CHO , Chul-Min LEE , Eun-Seok LEE
IPC分类号： G01R31/26
CPC分类号： G01R31/01 , G01R31/2894 , G01R31/31718
摘要： A method of testing a semiconductor device, which can reduce a period of time for testing a packaged semiconductor chip. First, semiconductor chips to be tested are classified in a lot unit. The semiconductor chips are fist tested in units of lots. The defective semiconductor chips among the semiconductor chips of a predetermined number of lots that are first time tested are collectively retested. First test data regarding the semiconductor chips may be classified and stored for each respective lot. Retest data regarding the semiconductor chips may be classified and stored for each respective lot. Test data regarding the semiconductor chips may be classified and stored into first test data and retest data for each respective lot.
摘要翻译：一种测试半导体器件的方法，其可以减少用于测试封装的半导体芯片的时间段。首先，要测试的半导体芯片分为多个单元。半导体芯片以单位批量进行了测试。首次测试的预定数量批次的半导体芯片中的有缺陷的半导体芯片被集体重新测试。关于半导体芯片的第一测试数据可以针对每个批次进行分类和存储。关于半导体芯片的重新测试数据可以针对每个批次进行分类和存储。可以将关于半导体芯片的测试数据分类并存储到第一测试数据中并且对于每个批次重新测试数据。

5. 发明申请

US20070290707A1 TEST SYSTEM OF SEMICONDUCTOR DEVICE HAVING A HANDLER REMOTE CONTROL AND METHOD OF OPERATING THE SAME 有权
标题翻译：具有操作者远程控制的半导体器件的测试系统及其操作方法
公开(公告)号：US20070290707A1
公开(公告)日：2007-12-20
申请号：US11749053
申请日：2007-05-15
申请人： Ae-Yong CHUNG , Eun-Seok LEE , Jeong-Ho BANG , Kyeong-Seon SHIN , Dae-Gab CHI , Sung-Ok KIM
发明人： Ae-Yong CHUNG , Eun-Seok LEE , Jeong-Ho BANG , Kyeong-Seon SHIN , Dae-Gab CHI , Sung-Ok KIM
IPC分类号： G01R31/00
CPC分类号： G01R31/2893 , G01R31/2894 , G01R31/31718 , G01R31/31919
摘要： A test system of a semiconductor device for a handler remote control is provided. The system includes: a tester for testing the semiconductor device; a handler connected to the tester through a GPIB (General Purpose Instruction Bus) communication cable; a tester server connected to the tester to download a test program, handler remote control program and a handler state check program to the tester; and communication data transmitted and received through the GPIB communication cable between the tester and the handler, wherein the communication data has basic communication data for an electrical test of the semiconductor device, communication data for the handler remote control, and communication data for a handler state check.
摘要翻译：提供了一种用于处理器遥控器的半导体器件的测试系统。该系统包括：用于测试半导体器件的测试仪; 通过GPIB（通用指令总线）通信电缆连接到测试仪的处理器; 连接到测试器的测试仪服务器向测试者下载测试程序，处理程序遥控程序和处理程序状态检查程序; 以及通过GPIB通信电缆在测试者和处理者之间发送和接收的通信数据，其中通信数据具有用于半导体器件的电气测试的基本通信数据，用于处理器远程控制的通信数据和用于处理器状态的通信数据检查。

6. 发明申请

US20080197874A1 TEST APPARATUS HAVING MULTIPLE TEST SITES AT ONE HANDLER AND ITS TEST METHOD 有权
标题翻译：具有多个测试站点的测试设备及其测试方法
公开(公告)号：US20080197874A1
公开(公告)日：2008-08-21
申请号：US12109299
申请日：2008-04-24
申请人： Ae-Yong CHUNG , Sung-Ok KIM , Kyeong-Seon SHIN , Jeong-Ho BANG
发明人： Ae-Yong CHUNG , Sung-Ok KIM , Kyeong-Seon SHIN , Jeong-Ho BANG
IPC分类号： G01R31/26
CPC分类号： G01R31/2893 , G01R31/01 , G01R31/2851
摘要： A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus.
摘要翻译：测试装置包括连接到测试器的一个处理器和分成两个或更多个站点或两个或更多个测试板的一个测试板。由于只有测试板（或测试板）上的站点需要复制，而不是处理器的加载通道或分拣机，所以测试设备可以方便地紧凑。此外，在一个站点或一个测试板上测试半导体器件时，可以根据测试结果对另一个站点中的另一个站点或另一个测试板上的半导体器件进行分类。这使得能够减少或消除测试器空闲时间以优化测试设备的效率。

7. 发明授权

US07408339B2 Test system of semiconductor device having a handler remote control and method of operating the same 有权
标题翻译：具有处理器遥控器的半导体器件的测试系统及其操作方法
公开(公告)号：US07408339B2
公开(公告)日：2008-08-05
申请号：US11749053
申请日：2007-05-15
申请人： Ae-Yong Chung , Eun-Seok Lee , Jeong-Ho Bang , Kyeong-Seon Shin , Dae-Gab Chi , Sung-Ok Kim
发明人： Ae-Yong Chung , Eun-Seok Lee , Jeong-Ho Bang , Kyeong-Seon Shin , Dae-Gab Chi , Sung-Ok Kim
IPC分类号： G01R31/28
CPC分类号： G01R31/2893 , G01R31/2894 , G01R31/31718 , G01R31/31919
摘要： A test system of a semiconductor device for a handler remote control is provided. The system includes: a tester for testing the semiconductor device; a handler connected to the tester through a GPIB (General Purpose Instruction Bus) communication cable; a tester server connected to the tester to download a test program, handler remote control program and a handler state check program to the tester; and communication data transmitted and received through the GPIB communication cable between the tester and the handler, wherein the communication data has basic communication data for an electrical test of the semiconductor device, communication data for the handler remote control, and communication data for a handler state check.
摘要翻译：提供了一种用于处理器遥控器的半导体器件的测试系统。该系统包括：用于测试半导体器件的测试仪; 通过GPIB（通用指令总线）通信电缆连接到测试仪的处理器; 连接到测试器的测试仪服务器向测试者下载测试程序，处理程序遥控程序和处理程序状态检查程序; 以及通过测试者和处理者之间的GPIB通信电缆发送和接收的通信数据，其中通信数据具有用于半导体器件的电气测试的基本通信数据，用于处理器远程控制的通信数据和用于处理器状态的通信数据检查。

8. 发明授权

US07378864B2 Test apparatus having multiple test sites at one handler and its test method 有权
标题翻译：在一个处理机上具有多个测试点的测试设备及其测试方法
公开(公告)号：US07378864B2
公开(公告)日：2008-05-27
申请号：US11092067
申请日：2005-03-28
申请人： Ae-Yong Chung , Sung-Ok Kim , Kyeong-Seon Shin , Jeong-Ho Bang
发明人： Ae-Yong Chung , Sung-Ok Kim , Kyeong-Seon Shin , Jeong-Ho Bang
IPC分类号： G01R31/26 , G01R31/28
CPC分类号： G01R31/2893 , G01R31/01 , G01R31/2851
摘要： A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus.
摘要翻译：测试装置包括连接到测试器的一个处理器和分成两个或更多个站点或两个或更多个测试板的一个测试板。由于只有测试板（或测试板）上的站点需要复制，而不是处理器的加载通道或分拣机，所以测试设备可以方便地紧凑。此外，在一个站点或一个测试板上测试半导体器件时，可以根据测试结果对另一个站点中的另一个站点或另一个测试板上的半导体器件进行分类。这使得能够减少或消除测试器空闲时间以优化测试设备的效率。

9. 发明授权

US07230417B2 Test system of semiconductor device having a handler remote control and method of operating the same 有权
标题翻译：具有处理器遥控器的半导体器件的测试系统及其操作方法
公开(公告)号：US07230417B2
公开(公告)日：2007-06-12
申请号：US11252448
申请日：2005-10-17
申请人： Ae-Yong Chung , Eun-Seok Lee , Jeong-Ho Bang , Kyeong-Seon Shin , Dae-Gab Chi , Sung-Ok Kim
发明人： Ae-Yong Chung , Eun-Seok Lee , Jeong-Ho Bang , Kyeong-Seon Shin , Dae-Gab Chi , Sung-Ok Kim
IPC分类号： G01R31/28
CPC分类号： G01R31/31926 , G01R31/31907
摘要： A test system of a semiconductor device for a handler remote control is provided. The system includes: a tester for testing the semiconductor device; a handler connected to the tester through a GPIB (General Purpose Instruction Bus) communication cable; a tester server connected to the tester to download a test program, handler remote control program and a handler state check program to the tester; and communication data transmitted and received through the GPIB communication cable between the tester and the handler, wherein the communication data has basic communication data for an electrical test of the semiconductor device, communication data for the handler remote control, and communication data for a handler state check.
摘要翻译：提供了一种用于处理器遥控器的半导体器件的测试系统。该系统包括：用于测试半导体器件的测试仪; 通过GPIB（通用指令总线）通信电缆连接到测试仪的处理器; 连接到测试器的测试仪服务器向测试者下载测试程序，处理程序遥控程序和处理程序状态检查程序; 以及通过GPIB通信电缆在测试者和处理者之间发送和接收的通信数据，其中通信数据具有用于半导体器件的电气测试的基本通信数据，用于处理器远程控制的通信数据和用于处理器状态的通信数据检查。

10. 发明申请

US20050168236A1 Test apparatus having multiple test sites at one handler and its test method 有权
标题翻译：在一个处理机上具有多个测试点的测试装置及其测试方法
公开(公告)号：US20050168236A1
公开(公告)日：2005-08-04
申请号：US11092067
申请日：2005-03-28
申请人： Ae-Yong Chung , Sung-Ok Kim , Kyeong-Seon Shin , Jeong-Ho Bang
发明人： Ae-Yong Chung , Sung-Ok Kim , Kyeong-Seon Shin , Jeong-Ho Bang
IPC分类号： G01R31/26 , G01R31/01 , G01R31/28
CPC分类号： G01R31/2893 , G01R31/01 , G01R31/2851
摘要： A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus.
摘要翻译：测试装置包括连接到测试器的一个处理器和分成两个或更多个站点或两个或更多个测试板的一个测试板。由于只有测试板（或测试板）上的站点需要复制，而不是处理器的加载通道或分拣机，所以测试设备可以方便地紧凑。此外，在一个站点或一个测试板上测试半导体器件时，可以根据测试结果对另一个站点中的另一个站点或另一个测试板上的半导体器件进行分类。这使得能够减少或消除测试器空闲时间以优化测试设备的效率。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式