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1. 发明申请

US20080288903A1 Generating testcases based on numbers of testcases previously generated 失效
标题翻译：根据以前生成的测试用例数生成测试用例
公开(公告)号：US20080288903A1
公开(公告)日：2008-11-20
申请号：US12220497
申请日：2008-07-24
申请人： Sundeep Chadha
发明人： Sundeep Chadha
IPC分类号： G06F17/50
CPC分类号： G06F11/263
摘要： An apparatus, computer system, and storage medium that, in an embodiment, receive elements and a goal for each of the elements. In various embodiments, the elements may represent commands or parameter values for a device to be tested. Testcases are generated based on the elements. If the numbers of testcases for the elements are equally distant from their goals, then a new testcase is generated based on an element chosen at random. But, if the numbers of testcases are not equally distant from their goals, then the new testcase is generated based on the element whose number of testcases if furthest from its respective goal. The number of testcases associated with the chosen element is then incremented, and the process is repeated. In this way, the generated testcases are based on the numbers of previously generated testcases, which, in an embodiment, results in more complete coverage of testcases for the device under test.
摘要翻译：在一个实施例中，接收元件和每个元件的目标的装置，计算机系统和存储介质。在各种实施例中，元件可以表示要测试的设备的命令或参数值。测试箱是基于元素生成的。如果这些元素的测试用例数量与其目标相同，则会根据随机选择的元素生成新的测试用例。但是，如果测试用例的数量与其目标不相等，那么新的测试用例将根据最大测试用例的元素生成。然后增加与所选元素相关联的测试用例数，并重复该过程。以这种方式，所生成的测试用例基于先前生成的测试用例的数量，在一个实施例中，测试用例可以对被测设备的测试箱进行更完整的覆盖。

2. 发明申请

US20070220390A1 Method and system for verifying equivalence of two representations of a stimulus pattern for testing a design 审中-公开
标题翻译：用于验证用于测试设计的刺激模式的两个表示的等价性的方法和系统
公开(公告)号：US20070220390A1
公开(公告)日：2007-09-20
申请号：US11367940
申请日：2006-03-04
申请人： Sarah Bird , Sundeep Chadha , Maureen Davis , Kirk Morrow , Tung Pham
发明人： Sarah Bird , Sundeep Chadha , Maureen Davis , Kirk Morrow , Tung Pham
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F17/5022
摘要： A method for verifying the equivalence of two representations of a stimulus pattern for testing a design is disclosed. The method includes receiving a base pattern file representing the stimulus pattern in a first file format. A derivative pattern file in a second file format is generated from the base pattern file. The derivative pattern file is parsed to create a first testing file in a third file format, and the first testing file is simulated against the design in a first simulation. Whether the first testing file passed the first simulation against the design is determined, and in response to determining that the first testing file does not pass the first simulation against the design, the base pattern file is parsed to create a second testing file in the third file format. The second testing file is simulated in a second simulation. Whether the second testing file passed the second simulation is determined, and, in response to determining that the second testing file passed the second simulation, a likely non-equivalence of the derivative pattern file and the base pattern file is indicated. In response to determining that the second testing file did not pass the second simulation, a likely equivalence of the derivative pattern file and the base pattern file is indicated.
摘要翻译：公开了一种用于验证用于测试设计的刺激图案的两个表示的等价性的方法。该方法包括以第一文件格式接收表示刺激图案的基本图案文件。从基本模式文件生成第二种文件格式的派生模式文件。解析派生模式文件以第三种文件格式创建第一个测试文件，并在第一次模拟中对第一个测试文件进行模拟。确定第一测试文件是否通过了针对设计的第一次仿真，并且响应于确定第一测试文件没有通过针对设计的第一测试文件，基础模式文件被解析以在第三测试文件中创建第二测试文件文件格式。第二个测试文件在第二个模拟中被模拟。确定第二测试文件是否通过第二模拟，并且响应于确定第二测试文件通过第二模拟，指示导数模式文件和基本模式文件的可能的非等价性。响应于确定第二测试文件没有通过第二模拟，指示导数模式文件和基本模式文件的可能等价。

3. 发明申请

US20060143582A1 Generating testcases based on numbers of testcases previously generated 失效
公开(公告)号：US20060143582A1
公开(公告)日：2006-06-29
申请号：US11021525
申请日：2004-12-23
申请人： Sundeep Chadha
发明人： Sundeep Chadha
IPC分类号： G06F17/50
CPC分类号： G06F11/263
摘要： A method, apparatus, system, and signal-bearing medium that, in an embodiment, receive elements and a goal for each of the elements. In various embodiments, the elements may represent commands or parameter values for a device to be tested. Testcases are generated based on the elements. If the numbers of testcases for the elements are equally distant from their goals, then a new testcase is generated based on an element chosen at random. But, if the numbers of testcases are not equally distant from their goals, then the new testcase is generated based on the element whose number of testcases if furthest from its respective goal. The number of testcases associated with the chosen element is then incremented, and the process is repeated. In this way, the generated testcases are based on the numbers of previously generated testcases, which, in an embodiment, results in more complete coverage of testcases for the device under test.

4. 发明申请

US20110276778A1 EFFICIENT SUPPORT OF MULTIPLE PAGE SIZE SEGMENTS 有权
标题翻译：有效支持多页尺寸段
公开(公告)号：US20110276778A1
公开(公告)日：2011-11-10
申请号：US12775652
申请日：2010-05-07
申请人： Miles R. Dooley , Sundeep Chadha , Naresh Nayar , Randal C. Swanberg
发明人： Miles R. Dooley , Sundeep Chadha , Naresh Nayar , Randal C. Swanberg
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/652
摘要： An apparatus, system, and method are disclosed for improved support of MPS segments in a microprocessor. The virtual address is used to generate possible TLB index values for each of the supported page sizes of the MPS segment associated with the virtual address. The possible TLB index values may be a hash generated using the virtual address and one of the supported page sizes. The TLB is searched for actual TLB index values that match the possible TLB index values calculated using the different supported page sizes. TLB entries associated with those actual TLB index values are checked to determine whether any TLB entry is associated with the virtual address. If no match is found, the real address is retrieved from the PT. The actual page size in the PT is used to generate an actual TLB index value for the virtual address and the TLB entry is inserted into the TLB.
摘要翻译：公开了一种用于改进对微处理器中的MPS段的支持的装置，系统和方法。虚拟地址用于为与虚拟地址相关联的MPS段的每个支持的页面大小生成可能的TLB索引值。可能的TLB索引值可以是使用虚拟地址和支持的页面大小之一生成的哈希值。搜索与使用不同的支持的页面大小计算的可能的TLB索引值相匹配的实际TLB索引值的TLB。检查与这些实际TLB索引值相关联的TLB条目以确定是否有任何TLB条目与虚拟地址相关联。如果没有找到匹配，则从PT检索真实地址。 PT中的实际页面大小用于生成虚拟地址的实际TLB索引值，并将TLB条目插入到TLB中。

5. 发明授权

US07853420B2 Performing temporal checking 有权
标题翻译：执行时间检查
公开(公告)号：US07853420B2
公开(公告)日：2010-12-14
申请号：US12102510
申请日：2008-04-14
申请人： Parag Birmiwal , Sundeep Chadha , Tilman Gloekler , Johannes Koesters
发明人： Parag Birmiwal , Sundeep Chadha , Tilman Gloekler , Johannes Koesters
IPC分类号： G06F17/50
CPC分类号： G01R31/318357 , G01R31/318328
摘要： An apparatus for performing temporal checking is disclosed. A signal logger for performing temporal checking includes a group of edge detection modules and a group of counting modules. During testing, the signal logger is coupled to a device under testing (DUT). Each of the edge detection modules is capable of maintaining edge information after a state transition on a signal within the DUT has been detected. Each of the counting modules is associated with one of the edge detection modules. Each of the countering modules is capable of maintaining a clock cycle count information associated with a detected edge. After the testing has been completed, temporal checking information on a signal within the DUT can be obtained by reconstructing the edge information and the associated clock cycle count information of the signal collected during the test.
摘要翻译：公开了一种用于进行时间检查的装置。用于执行时间检查的信号记录器包括一组边缘检测模块和一组计数模块。在测试期间，信号记录器耦合到被测设备（DUT）。每个边缘检测模块能够在检测到DUT内的信号的状态转换之后保持边缘信息。每个计数模块与边缘检测模块之一相关联。每个对抗模块能够维持与检测到的边缘相关联的时钟周期计数信息。在测试完成之后，可以通过重建在测试期间收集的信号的边缘信息和相关联的时钟周期计数信息来获得DUT内的信号的时间检查信息。

6. 发明授权

US07516430B2 Generating testcases based on numbers of testcases previously generated 失效
标题翻译：根据以前生成的测试用例数生成测试用例
公开(公告)号：US07516430B2
公开(公告)日：2009-04-07
申请号：US11021525
申请日：2004-12-23
申请人： Sundeep Chadha
发明人： Sundeep Chadha
IPC分类号： G06F17/50 , G06F17/10
CPC分类号： G06F11/263
摘要： A method, apparatus, system, and signal-bearing medium that, in an embodiment, receive elements and a goal for each of the elements. In various embodiments, the elements may represent commands or parameter values for a device to be tested. Testcases are generated based on the elements. If the numbers of testcases for the elements are equally distant from their goals, then a new testcase is generated based on an element chosen at random. But, if the numbers of testcases are not equally distant from their goals, then the new testcase is generated based on the element whose number of testcases if furthest from its respective goal. The number of testcases associated with the chosen element is then incremented, and the process is repeated. In this way, the generated testcases are based on the numbers of previously generated testcases, which, in an embodiment, results in more complete coverage of testcases for the device under test.
摘要翻译：在一个实施例中，接收每个元件的元件和目标的方法，装置，系统和信号承载介质。在各种实施例中，元件可以表示要测试的设备的命令或参数值。测试箱是基于元素生成的。如果这些元素的测试用例数量与其目标相同，则会根据随机选择的元素生成新的测试用例。但是，如果测试用例的数量与其目标不相等，那么新的测试用例将根据最大测试用例的元素生成。然后增加与所选元素相关联的测试用例数，并重复该过程。以这种方式，所生成的测试用例基于先前生成的测试用例的数量，在一个实施例中，测试用例可以对被测设备的测试箱进行更完整的覆盖。

7. 发明授权

US07464354B2 Method and apparatus for performing temporal checking 有权
标题翻译：执行时间检查的方法和装置
公开(公告)号：US07464354B2
公开(公告)日：2008-12-09
申请号：US11297308
申请日：2005-12-08
申请人： Parag Birmiwal , Sundeep Chadha , Tilman Gloekler , Johannes Koesters
发明人： Parag Birmiwal , Sundeep Chadha , Tilman Gloekler , Johannes Koesters
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G01R31/318357 , G01R31/318328
摘要： An apparatus for performing temporal checking is disclosed. A signal logger for performing temporal checking includes a group of edge detection modules and a group of counting modules. During testing, the signal logger is coupled to a device under testing (DUT). Each of the edge detection modules is capable of maintaining edge information after a state transition on a signal within the DUT has been detected. Each of the counting modules is associated with one of the edge detection modules. Each of the countering modules is capable of maintaining a clock cycle count information associated with a detected edge. After the testing has been completed, temporal checking information on a signal within the DUT can be obtained by reconstructing the edge information and the associated clock cycle count information of the signal collected during the test.
摘要翻译：公开了一种用于进行时间检查的装置。用于执行时间检查的信号记录器包括一组边缘检测模块和一组计数模块。在测试期间，信号记录器耦合到被测设备（DUT）。每个边缘检测模块能够在检测到DUT内的信号的状态转换之后保持边缘信息。每个计数模块与边缘检测模块之一相关联。每个对抗模块能够维持与检测到的边缘相关联的时钟周期计数信息。在测试完成之后，可以通过重建在测试期间收集的信号的边缘信息和相关联的时钟周期计数信息来获得DUT内的信号的时间检查信息。

8. 发明申请

US20080195340A1 Performing temporal checking 审中-公开
标题翻译：执行时间检查
公开(公告)号：US20080195340A1
公开(公告)日：2008-08-14
申请号：US12102525
申请日：2008-04-14
申请人： Parag Birmiwal , Sundeep Chadha , Tilman Gloekler , Johannes Koesters
发明人： Parag Birmiwal , Sundeep Chadha , Tilman Gloekler , Johannes Koesters
IPC分类号： G01R31/00
CPC分类号： G01R31/318357 , G01R31/318328
摘要： An apparatus for performing temporal checking is disclosed. A signal logger for performing temporal checking includes a group of edge detection modules and a group of counting modules. During testing, the signal logger is coupled to a device under testing (DUT). Each of the edge detection modules is capable of maintaining edge information after a state transition on a signal within the DUT has been detected. Each of the counting modules is associated with one of the edge detection modules. Each of the countering modules is capable of maintaining a clock cycle count information associated with a detected edge. After the testing has been completed, temporal checking information on a signal within the DUT can be obtained by reconstructing the edge information and the associated clock cycle count information of the signal collected during the test.
摘要翻译：公开了一种用于进行时间检查的装置。用于执行时间检查的信号记录器包括一组边缘检测模块和一组计数模块。在测试期间，信号记录器耦合到被测设备（DUT）。每个边缘检测模块能够在检测到DUT内的信号的状态转换之后保持边缘信息。每个计数模块与边缘检测模块之一相关联。每个对抗模块能够维持与检测到的边缘相关联的时钟周期计数信息。在测试完成之后，可以通过重建在测试期间收集的信号的边缘信息和相关联的时钟周期计数信息来获得DUT内的信号的时间检查信息。

9. 发明申请

US20060179182A1 Data communication method and apparatus utilizing programmable channels for allocation of buffer space and transaction control 失效
公开(公告)号：US20060179182A1
公开(公告)日：2006-08-10
申请号：US11047548
申请日：2005-01-31
申请人： Sundeep Chadha , Mark Check , Bernard Drerup , Michael Grassi
发明人： Sundeep Chadha , Mark Check , Bernard Drerup , Michael Grassi
IPC分类号： G06F3/00
CPC分类号： G06F13/4059
摘要： A control mechanism for data bus communications employs channels to which bus transactions are assigned, each channel having independent flow control. The control mechanism enforces an ordering algorithm among channels, whereby at least some transactions may pass other transactions. Channel attributes are programmable to vary the ordering conditions. Preferably, each channel is allocated its own programmable buffer area. The control mechanism independently determines, for each channel, whether buffer space is available and enforces flow control independently for each channel accordingly. Flow control is preferably credit-based, credits representing buffer space or some other capacity of a receiver to receive data. Preferably, the flow control mechanism comprises a central interconnect module controlling internal communications of an integrated circuit chip.

10. 发明授权

US08745307B2 Multiple page size segment encoding 有权
标题翻译：多页大小段编码
公开(公告)号：US08745307B2
公开(公告)日：2014-06-03
申请号：US12779563
申请日：2010-05-13
申请人： Sundeep Chadha , Cathy May , Naresh Nayar , Randal Craig Swanberg
发明人： Sundeep Chadha , Cathy May , Naresh Nayar , Randal Craig Swanberg
IPC分类号： G06F12/00 , G06F12/10
CPC分类号： G06F12/1018 , G06F12/1009 , G06F12/1027 , G06F12/1036 , G06F2212/652
摘要： An approach identifies an amount of high order bits used to store a memory address in a memory address field that is included in a memory. This approach calculates at least one minimum number of low order bits not used to store the address with the calculation being based on the identified amount of high order bits. The approach retrieves a data element from one of the identified minimum number of low order bits of the address field and also retrieves a second data element from one of the one of the identified minimum number of low order bits of the address field.
摘要翻译：一种方法识别用于在存储器中包括的存储器地址字段中存储存储器地址的高位数量。该方法计算不用于存储地址的至少一个最低数量的低阶位，其中计算基于所识别的高位位数。该方法从所识别的地址字段的最低位数的最低位数中的一个中检索数据元素，并且还从所识别的地址字段的最低位数中的一个中检索第二数据元素。

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