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1. 发明授权

US08977995B1 Timing budgeting of nested partitions for hierarchical integrated circuit designs 有权
标题翻译：用于分层集成电路设计的嵌套分区的时序预算
公开(公告)号：US08977995B1
公开(公告)日：2015-03-10
申请号：US13586495
申请日：2012-08-15
申请人： Sumit Arora , Oleg Levitsky , Amit Kumar , Sushobhit Singh
发明人： Sumit Arora , Oleg Levitsky , Amit Kumar , Sushobhit Singh
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： In one embodiment, a method of designing an integrated circuit is disclosed, including receiving a plurality of top level timing constraints and a description of the integrated circuit design defining a hierarchy of partitions having multiple levels with one or more nested partitions; generating timing models for each partition of the plurality of partitions in response to the description of the integrated circuit design; and concurrently generating timing budgets level by level for all partitions at each level, beginning with the lowest level to each next upper level of the hierarchy of the partitions in response to the description of the integrated circuit design, the timing models, and the plurality of top level timing constraints. Please see the detailed description and claims for other embodiments that are respectively disclosed and claimed.
摘要翻译：在一个实施例中，公开了一种设计集成电路的方法，包括接收多个顶层定时约束和对使用一个或多个嵌套分区具有多个层次的分区的层次结构的集成电路设计的描述; 响应于所述集成电路设计的描述，为所述多个分区的每个分区生成定时模型; 并且响应于对集成电路设计，定时模型和多个等级的描述，从每个级别的所有分区逐级生成定时预算，从分区的层次结构的最下一级开始到每个下一个较高级别顶级时间约束。请参阅分别披露和要求保护的其他实施例的详细描述和权利要求。

2. 发明授权

US07865857B1 System and method for improved visualization and debugging of constraint circuit objects 有权
标题翻译：用于改进约束电路对象可视化和调试的系统和方法
公开(公告)号：US07865857B1
公开(公告)日：2011-01-04
申请号：US11657659
申请日：2007-01-23
申请人： Amit Chopra , Ian Gebbie , Donald O'Riordan , Sumit Arora , Jean-Daniel Sonnard
发明人： Amit Chopra , Ian Gebbie , Donald O'Riordan , Sumit Arora , Jean-Daniel Sonnard
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5068
摘要： Features are provided for graphically representing constraints on design objects in an Electronic Design Automation tool. A particular constraint on one or more circuit objects is displayed as a highlighted region that extends to each visible circuit object to which the constraint applies. Attributes of the highlighted region, such as density and thickness, may proportionally represent attributes of the constraint, such as a strength or distance specified by the constraint. The highlighted region is superimposed on or around circuit objects. The highlighted region may be a halo, which is a partially transparent region filled with a color. Multiple regions that represent the same type of constraint or relationship are connected by line segments, providing the ability to visualize groups of constrained objects, including groups that span levels of a hierarchical design. Intersecting highlighted regions are blended together using techniques such as alpha blending.
摘要翻译：提供了在电子设计自动化工具中图形化表示设计对象约束的特性。对一个或多个电路对象的特定约束被显示为突出显示的区域，其延伸到约束所适用的每个可见电路对象。突出显示区域的属性（如密度和厚度）可以成比例地表示约束的属性，例如由约束指定的强度或距离。突出显示的区域叠加在电路对象上或周围。突出显示的区域可以是光晕，其是填充有颜色的部分透明区域。表示相同类型的约束或关系的多个区域通过线段连接，提供了可视化约束对象组的能力，包括跨层次设计层次的组。使用诸如α混合的技术将相交突出显示的区域混合在一起。

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