专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08539412B2 Macro layout verification appartus 有权
标题翻译：宏布局验证配件
公开(公告)号：US08539412B2
公开(公告)日：2013-09-17
申请号：US13618553
申请日：2012-09-14
申请人： Masashi Arayama , Sumiko Makino
发明人： Masashi Arayama , Sumiko Makino
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077 , G06F17/5081 , H01L27/0203
摘要： A macro layout verification apparatus for verifying a layout of a macro to be placed as a functional block on a semiconductor device. The apparatus includes: a unit, which assumes as a virtual wiring line, a wiring line that uses an unused intra-macro channel located adjacent to an intra-macro wiring line; a unit which calculates a parallel wiring length along which the virtual wiring line and the intra-macro wiring line run; and a unit which outputs information concerning the virtual wiring line when the parallel wiring length exceeds a reference value defined as a design rule.
摘要翻译：一种宏观布局验证装置，用于验证要在半导体器件上作为功能块放置的宏的布局。该装置包括：假定为虚拟布线的单元，使用位于宏观布线附近的未使用的宏块内通道的布线; 计算出虚拟布线和宏观布线运行的平行布线长度的单元; 以及当平行布线长度超过被定义为设计规则的参考值时输出关于虚拟布线的信息的单元。

2. 发明申请

US20130014067A1 MACRO LAYOUT VERIFICATION APPARTUS 有权
标题翻译： MACRO布局验证APPARTUS
公开(公告)号：US20130014067A1
公开(公告)日：2013-01-10
申请号：US13618553
申请日：2012-09-14
申请人： Masashi Arayama , Sumiko Makino
发明人： Masashi Arayama , Sumiko Makino
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077 , G06F17/5081 , H01L27/0203
摘要： A macro layout verification apparatus for verifying a layout of a macro to be placed as a functional block on a semiconductor device. The apparatus includes: a unit, which assumes as a virtual wiring line, a wiring line that uses an unused intra-macro channel located adjacent to an intra-macro wiring line; a unit which calculates a parallel wiring length along which the virtual wiring line and the intra-macro wiring line run; and a unit which outputs information concerning the virtual wiring line when the parallel wiring length exceeds a reference value defined as a design rule.
摘要翻译：一种宏观布局验证装置，用于验证要在半导体器件上作为功能块放置的宏的布局。该装置包括：假定为虚拟布线的单元，使用位于宏观布线附近的未使用的宏块内通道的布线; 计算虚拟布线和宏观布线运行的平行布线长度的单元; 以及当平行布线长度超过被定义为设计规则的参考值时输出关于虚拟布线的信息的单元。

3. 发明申请

US20120284681A1 CIRCUIT DESIGNING METHOD AND CIRCUIT DESIGNING SYSTEM 失效
标题翻译：电路设计方法和电路设计系统
公开(公告)号：US20120284681A1
公开(公告)日：2012-11-08
申请号：US13550940
申请日：2012-07-17
申请人： Sumiko MAKINO , Yasuo AMANO
发明人： Sumiko MAKINO , Yasuo AMANO
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/04
摘要： A circuit designing method designs a circuit by client computers designing blocks forming the circuit in parallel, and a server exchanging information in real-time with each client computer. The method may notify information related to blocks corresponding to a request from each client computer to the server, analyze each block by an analyzing tool based on the acquired information, and when an analysis result includes an error, compute by a modification ease computing tool, a modification ease of an arbitrary block that includes the error, to notify each client computer of an analysis result taking into consideration the modification ease.
摘要翻译：电路设计方法通过客户端计算机设计并行设计形成电路的块的电路，以及服务器与每个客户端计算机实时交换信息。该方法可以将与来自每个客户计算机的请求相对应的块的信息通知给服务器，基于所获取的信息通过分析工具分析每个块，并且当分析结果包括错误时，通过修改易用性计算工具进行计算，包括错误的任意块的修改容易性，考虑到修改容易性，向每个客户端计算机通知分析结果。

4. 发明申请

US20100235797A1 MACRO LAYOUT VERIFICATION APPARATUS 有权
标题翻译：大型布局验证装置
公开(公告)号：US20100235797A1
公开(公告)日：2010-09-16
申请号：US12785624
申请日：2010-05-24
申请人： Masashi ARAYAMA , Sumiko Makino
发明人： Masashi ARAYAMA , Sumiko Makino
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077 , G06F17/5081 , H01L27/0203
摘要： A macro layout verification apparatus for verifying a layout of a macro to be placed as a functional block on a semiconductor device. The apparatus includes: a unit, which assumes as a virtual wiring line, a wiring line that uses an unused intra-macro channel located adjacent to an intra-macro wiring line; a unit which calculates a parallel wiring length along which the virtual wiring line and the intra-macro wiring line run; and a unit which outputs information concerning the virtual wiring line when the parallel wiring length exceeds a reference value defined as a design rule.
摘要翻译：一种宏观布局验证装置，用于验证要在半导体器件上作为功能块放置的宏的布局。该装置包括：假定为虚拟布线的单元，使用位于宏观布线附近的未使用的宏块内通道的布线; 计算出虚拟布线和宏观布线运行的平行布线长度的单元; 以及当平行布线长度超过被定义为设计规则的参考值时输出关于虚拟布线的信息的单元。

5. 发明授权

US08453077B2 Circuit designing method and circuit designing system 失效
标题翻译：电路设计方法和电路设计系统
公开(公告)号：US08453077B2
公开(公告)日：2013-05-28
申请号：US13550940
申请日：2012-07-17
申请人： Sumiko Makino , Yasuo Amano
发明人： Sumiko Makino , Yasuo Amano
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/04
摘要： A circuit designing method designs a circuit by client computers designing blocks forming the circuit in parallel, and a server exchanging information in real-time with each client computer. The method may notify information related to blocks corresponding to a request from each client computer to the server, analyze each block by an analyzing tool based on the acquired information, and when an analysis result includes an error, compute by a modification ease computing tool, a modification ease of an arbitrary block that includes the error, to notify each client computer of an analysis result taking into consideration the modification ease.
摘要翻译：电路设计方法通过客户端计算机设计并行设计形成电路的块的电路，以及服务器与每个客户端计算机实时交换信息。该方法可以将与来自每个客户计算机的请求相对应的块的信息通知给服务器，基于所获取的信息通过分析工具分析每个块，并且当分析结果包括错误时，通过修改易用性计算工具进行计算，包括错误的任意块的修改容易性，考虑到修改容易性，向每个客户端计算机通知分析结果。

6. 发明授权

US08286117B2 Macro layout verification apparatus to detect error when connecting macro terminal in LSI design layout 有权
标题翻译：用于在LSI设计布局中连接宏终端时检测错误的宏布局验证装置
公开(公告)号：US08286117B2
公开(公告)日：2012-10-09
申请号：US12785624
申请日：2010-05-24
申请人： Masashi Arayama , Sumiko Makino
发明人： Masashi Arayama , Sumiko Makino
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077 , G06F17/5081 , H01L27/0203
摘要： A macro layout verification apparatus for verifying a layout of a macro to be placed as a functional block on a semiconductor device. The apparatus includes: a unit, which assumes as a virtual wiring line, a wiring line that uses an unused intra-macro channel located adjacent to an intra-macro wiring line; a unit which calculates a parallel wiring length along which the virtual wiring line and the intra-macro wiring line run; and a unit which outputs information concerning the virtual wiring line when the parallel wiring length exceeds a reference value defined as a design rule.
摘要翻译：一种宏观布局验证装置，用于验证要在半导体器件上作为功能块放置的宏的布局。该装置包括：假定为虚拟布线的单元，使用位于宏观布线附近的未使用的宏块内通道的布线; 计算出虚拟布线和宏观布线运行的平行布线长度的单元; 以及当平行布线长度超过被定义为设计规则的参考值时输出关于虚拟布线的信息的单元。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式