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1. 发明授权

US08866293B2 Semiconductor structure and fabrication method thereof 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08866293B2
公开(公告)日：2014-10-21
申请号：US13167086
申请日：2011-06-23
申请人： Yi-Hung Lin , Meng-Tsung Lee , Sui-An Kao , Yi-Hsin Chen , Feng-Lung Chien
发明人： Yi-Hung Lin , Meng-Tsung Lee , Sui-An Kao , Yi-Hsin Chen , Feng-Lung Chien
IPC分类号： H01L23/48 , H01L23/00 , H01L23/31
CPC分类号： H01L24/11 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/0345 , H01L2224/0361 , H01L2224/03622 , H01L2224/039 , H01L2224/03901 , H01L2224/03903 , H01L2224/03912 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05166 , H01L2224/0556 , H01L2224/05564 , H01L2224/05572 , H01L2224/05647 , H01L2224/11462 , H01L2224/116 , H01L2224/11849 , H01L2224/119 , H01L2224/13082 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2924/00014 , H01L2924/01022 , H01L2924/01029 , H01L2924/0132 , H01L2924/01074 , H01L2924/014 , H01L2224/0347 , H01L2224/1161 , H01L2224/05552
摘要： A semiconductor structure includes a semiconductor chip having at least an electrode pad, a first metal layer formed on the electrode pad, a second metal layer completely formed on and in contact with the first metal layer, and a conductive pillar disposed on the second metal layer, where a material of the first metal layer is different from a material of the second metal layer, the first metal layer has a first distribution-projected area larger than a second distribution projected-area of the conductive pillar, and the second metal layer has a third distribution-projected area that is the same as the second distribution-projected area of the conductive pillar.
摘要翻译：半导体结构包括具有至少电极焊盘，形成在电极焊盘上的第一金属层，完全形成在第一金属层上并与第一金属层接触的第二金属层的半导体芯片和设置在第二金属层上的导电柱其中，所述第一金属层的材料与所述第二金属层的材料不同，所述第一金属层具有大于所述导电柱的第二分布投影面积的第一分布投影面积，并且所述第二金属层具有与导电柱的第二分布投影面积相同的第三分布投影面积。

2. 发明授权

US08772922B2 Chip structure having redistribution layer 有权
标题翻译：具有再分配层的芯片结构
公开(公告)号：US08772922B2
公开(公告)日：2014-07-08
申请号：US13349051
申请日：2012-01-12
申请人： Hung-Yuan Hsu , Sui-An Kao
发明人： Hung-Yuan Hsu , Sui-An Kao
IPC分类号： H01L21/44 , H01L21/461 , H01L21/302
CPC分类号： H01L23/3171 , H01L24/02 , H01L2224/0235 , H01L2224/02377 , H01L2224/0239 , H01L2224/024 , H01L2924/01005 , H01L2924/01006 , H01L2924/01079
摘要： A chip structure having a redistribution layer includes: a chip with electrode pads disposed on an active surface thereof; a first passivation layer formed on the active surface and the electrode pads; a redistribution layer formed on the first passivation layer and having a plurality of wiring units, wherein each of the wiring units has a conductive pad, a conductive via and a conductive trace connecting the conductive pad and the conductive via, the conductive trace having at least a first through opening for exposing a portion of the first passivation layer; and a second passivation layer disposed on the first passivation layer and the redistribution layer, the second passivation layer being filled in the first through opening such that the first and second passivation layers are bonded to each other with the conductive trace sandwiched therebetween, thereby preventing delamination of the conductive trace from the second passivation layer.
摘要翻译：具有再分配层的芯片结构包括：具有设置在其活性表面上的电极焊盘的芯片; 形成在所述有源表面和所述电极焊盘上的第一钝化层; 形成在所述第一钝化层上并具有多个布线单元的再分配层，其中每个所述布线单元具有导电焊盘，导电孔和连接所述导电焊盘和所述导电通孔的导电迹线，所述导电迹线至少具有用于暴露第一钝化层的一部分的第一通孔; 以及设置在所述第一钝化层和所述再分布层上的第二钝化层，所述第二钝化层填充在所述第一通孔中，使得所述第一钝化层和所述第二钝化层彼此接合，导电迹线夹在其间，从而防止分层的来自第二钝化层的导电迹线。

3. 发明申请

US20120112363A1 CHIP STRUCTURE HAVING REDISTRIBUTION LAYER 有权
标题翻译：具有重新分配层的芯片结构
公开(公告)号：US20120112363A1
公开(公告)日：2012-05-10
申请号：US13349051
申请日：2012-01-12
申请人： Hung-Yuan Hsu , Sui-An Kao
发明人： Hung-Yuan Hsu , Sui-An Kao
IPC分类号： H01L23/48
CPC分类号： H01L23/3171 , H01L24/02 , H01L2224/0235 , H01L2224/02377 , H01L2224/0239 , H01L2224/024 , H01L2924/01005 , H01L2924/01006 , H01L2924/01079
摘要： A chip structure having a redistribution layer includes: a chip with electrode pads disposed on an active surface thereof; a first passivation layer formed on the active surface and the electrode pads; a redistribution layer formed on the first passivation layer and having a plurality of wiring units, wherein each of the wiring units has a conductive pad, a conductive via and a conductive trace connecting the conductive pad and the conductive via, the conductive trace having at least a first through opening for exposing a portion of the first passivation layer; and a second passivation layer disposed on the first passivation layer and the redistribution layer, the second passivation layer being filled in the first through opening such that the first and second passivation layers are bonded to each other with the conductive trace sandwiched therebetween, thereby preventing delamination of the conductive trace from the second passivation layer.
摘要翻译：具有再分配层的芯片结构包括：具有设置在其活性表面上的电极焊盘的芯片; 形成在所述有源表面和所述电极焊盘上的第一钝化层; 形成在所述第一钝化层上并具有多个布线单元的再分配层，其中每个所述布线单元具有导电焊盘，导电孔和连接所述导电焊盘和所述导电通孔的导电迹线，所述导电迹线至少具有用于暴露第一钝化层的一部分的第一通孔; 以及设置在所述第一钝化层和所述再分布层上的第二钝化层，所述第二钝化层填充在所述第一通孔中，使得所述第一钝化层和所述第二钝化层彼此接合，导电迹线夹在其间，从而防止分层的来自第二钝化层的导电迹线。

4. 发明申请

US20120280384A1 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20120280384A1
公开(公告)日：2012-11-08
申请号：US13167086
申请日：2011-06-23
申请人： Yi-Hung Lin , Meng-Tsung Lee , Sui-An Kao , Yi-Hsin Chen , Feng-Lung Chien
发明人： Yi-Hung Lin , Meng-Tsung Lee , Sui-An Kao , Yi-Hsin Chen , Feng-Lung Chien
IPC分类号： H01L23/48 , H01L21/283
CPC分类号： H01L24/11 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/0345 , H01L2224/0361 , H01L2224/03622 , H01L2224/039 , H01L2224/03901 , H01L2224/03903 , H01L2224/03912 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05166 , H01L2224/0556 , H01L2224/05564 , H01L2224/05572 , H01L2224/05647 , H01L2224/11462 , H01L2224/116 , H01L2224/11849 , H01L2224/119 , H01L2224/13082 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2924/00014 , H01L2924/01022 , H01L2924/01029 , H01L2924/0132 , H01L2924/01074 , H01L2924/014 , H01L2224/0347 , H01L2224/1161 , H01L2224/05552
摘要： A fabrication method of a semiconductor structure includes providing a chip having at least an electrode pad, forming a titanium layer on the electrode pad, forming a dielectric layer on the chip and a portion of the titanium layer, forming a copper layer on the dielectric layer and the titanium layer, forming a conductive pillar on the copper layer corresponding in position to the titanium layer, and removing a portion of the copper layer that is not covered by the conductive pillar. When the portion of the copper layer is removed by etching, undercutting of the titanium layer is avoided since the titanium layer is covered by the dielectric layer, thereby providing an improved support for the conductive pillar to increase product reliability.
摘要翻译：半导体结构的制造方法包括提供至少具有电极焊盘的芯片，在电极焊盘上形成钛层，在芯片上形成电介质层和钛层的一部分，在电介质层上形成铜层和钛层，在与铜层相对应的铜层上形成导电柱，并除去未被导电柱覆盖的铜层的一部分。当通过蚀刻去除铜层的部分时，由于钛层被电介质层覆盖，所以避免了钛层的底切，从而为导电柱提供改进的支撑以提高产品的可靠性。

5. 发明授权

US08097491B1 Chip structure having redistribution layer and fabrication method thereof 有权
标题翻译：具有再分布层的芯片结构及其制造方法
公开(公告)号：US08097491B1
公开(公告)日：2012-01-17
申请号：US12962326
申请日：2010-12-07
申请人： Hung-Yuan Hsu , Sui-An Kao
发明人： Hung-Yuan Hsu , Sui-An Kao
IPC分类号： H01L21/50 , H01L21/48 , H01L21/44
CPC分类号： H01L23/3171 , H01L24/02 , H01L2224/0235 , H01L2224/02377 , H01L2224/0239 , H01L2224/024 , H01L2924/01005 , H01L2924/01006 , H01L2924/01079
摘要： A chip structure having a redistribution layer includes: a chip with electrode pads disposed on an active surface thereof; a first passivation layer formed on the active surface and the electrode pads; a redistribution layer formed on the first passivation layer and having a plurality of wiring units, wherein each of the wiring units has a conductive pad, a conductive via and a conductive trace connecting the conductive pad and the conductive via, the conductive trace having at least a first through opening for exposing a portion of the first passivation layer; and a second passivation layer disposed on the first passivation layer and the redistribution layer, the second passivation layer being filled in the first through opening such that the first and second passivation layers are bonded to each other with the conductive trace sandwiched therebetween, thereby preventing delamination of the conductive trace from the second passivation layer.
摘要翻译：具有再分配层的芯片结构包括：具有设置在其活性表面上的电极焊盘的芯片; 形成在所述有源表面和所述电极焊盘上的第一钝化层; 形成在所述第一钝化层上并具有多个布线单元的再分配层，其中每个所述布线单元具有导电焊盘，导电孔和连接所述导电焊盘和所述导电通孔的导电迹线，所述导电迹线至少具有用于暴露第一钝化层的一部分的第一通孔; 以及设置在所述第一钝化层和所述再分布层上的第二钝化层，所述第二钝化层填充在所述第一通孔中，使得所述第一钝化层和所述第二钝化层彼此接合，导电迹线夹在其间，从而防止分层的来自第二钝化层的导电迹线。

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