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1. 发明授权

US07536566B2 System architecture for a power distribution network and method of operation 有权
标题翻译：配电网络的系统架构及运行方式
公开(公告)号：US07536566B2
公开(公告)日：2009-05-19
申请号：US11234899
申请日：2005-09-26
申请人： Steven M. Hemmah , Robert A. Neidorff , Jonathan M. Bearfield
发明人： Steven M. Hemmah , Robert A. Neidorff , Jonathan M. Bearfield
IPC分类号： G06F1/00
CPC分类号： H04L12/10
摘要： Digital and analog functionality are separated and optimized in an Ethernet port architecture to free port circuit space for additional desired functionality. A power controller and physical link controller for the port share a high speed communication link to transfer information and control instructions from one to the other. The physical link controller provides digital functionality and processing capabilities that can generate power control instructions sent to the power controller over the high speed link. The power controller provides analog functionality for controlling the power supplied to the network connection and transfers power related information to the physical link controller over the high speed communication link and receives control instructions through a digital interface. The separation of digital of analog functionality simplifies the power control circuitry, removes redundancy, and frees valuable circuit board space for other desired functionality.
摘要翻译：数字和模拟功能在以太网端口架构中分离和优化，以便为端口电路空间提供额外的所需功能。用于端口的功率控制器和物理链路控制器共享高速通信链路，以将信息和控制指令从一个传输到另一个。物理链路控制器提供数字功能和处理能力，可以生成通过高速链路发送到功率控制器的功率控制指令。功率控制器提供用于控制提供给网络连接的功率的模拟功能，并通过高速通信链路将功率相关信息传送到物理链路控制器，并通过数字接口接收控制指令。模拟功能的数字分离简化了电源控制电路，消除了冗余，并为其他所需的功能释放了有价值的电路板空间。

2. 发明授权

US5179030A Method of fabricating a buried zener diode simultaneously with other semiconductor devices 失效
标题翻译：与其他半导体器件同时制造埋地齐纳二极管的方法
公开(公告)号：US5179030A
公开(公告)日：1993-01-12
申请号：US692013
申请日：1991-04-26
申请人： Steven M. Hemmah
发明人： Steven M. Hemmah
IPC分类号： H01L21/329 , H01L21/8222 , H01L27/06 , H01L29/866
CPC分类号： H01L29/66106 , H01L21/8222 , H01L27/0664 , H01L29/866 , Y10S438/983
摘要： A method for fabricating a buried zener diode concurrently with other semiconductor devices on a large scale semiconductor wafer includes utilizing a composite mask to define one or more stable buried zener diodes, one or more additional semiconductor devices, and a number of isolation regions. After applying a screen oxide over selected portions of the semiconductor wafer, subsequent ion implantation steps and additional masking steps concurrently form the stable buried zener diode along with additional and different semiconductor devices utilizing conventional ion implant bi-polar processing techniques.
摘要翻译：与大规模半导体晶片上的其它半导体器件同时制造掩埋齐纳二极管的方法包括利用复合掩模来限定一个或多个稳定的掩埋齐纳二极管，一个或多个附加的半导体器件和多个隔离区域。在半导体晶片的选定部分上施加屏幕氧化物之后，随后的离子注入步骤和附加的掩模步骤同时利用常规离子注入双极处理技术与附加和不同的半导体器件一起形成稳定的掩埋齐纳二极管。

3. 发明授权

US4771011A Ion-implanted process for forming IC wafer with buried-Zener diode and IC structure made with such process 失效
标题翻译：用埋入齐纳二极管形成IC晶圆的离子注入工艺和采用这种工艺制成的IC结构
公开(公告)号：US4771011A
公开(公告)日：1988-09-13
申请号：US60765
申请日：1987-06-10
申请人： Steven M. Hemmah , Richard S. Payne
发明人： Steven M. Hemmah , Richard S. Payne
IPC分类号： H01L21/265 , H01L29/866 , H01L21/223
CPC分类号： H01L21/26513 , H01L29/866 , Y10S438/983
摘要： A new process making it possible to produce stable buried Zener diodes in large-sized wafers where slow ramping of diffusion temperatures is required to avoid crystal damage and other adverse effects. The process includes an initial deep ion implantation of p type dopant (boron). A second ion implantation of n type dopant (arsenic) is made over the p type implantation. Both implantations are driven in to the required degree. An additional p type dopant diffusion is made coincident with the base formation by ion implantation to establish connection to the original deep p-doped region, and an additional n type dopant diffusion is made coincident with the emitter formation to establish connection with the n type dopant implantation.
摘要翻译：一种新的工艺使得可以在大尺寸晶片中生产稳定的内置齐纳二极管，其中需要缓慢的扩散温度梯度以避免晶体损坏和其他不利影响。该方法包括p型掺杂剂（硼）的初始深离子注入。在p型注入上进行n型掺杂剂（砷）的第二离子注入。两种植入都被驱动到所需的程度。通过离子注入使另外的p型掺杂剂扩散与基底形成一致，以建立与原始深p掺杂区的连接，并且使附加的n型掺杂剂扩散与发射极形成一致以建立与n型掺杂物的连接植入。

4. 发明授权

US4601760A Ion-implanted process for forming IC wafer with buried-reference diode and IC structure made with such process 失效
标题翻译：用埋入参考二极管形成IC晶片的离子注入工艺和用这种工艺制成的IC结构
公开(公告)号：US4601760A
公开(公告)日：1986-07-22
申请号：US776469
申请日：1985-09-16
申请人： Steven M. Hemmah , Richard S. Payne
发明人： Steven M. Hemmah , Richard S. Payne
IPC分类号： H01L21/265 , H01L29/866 , H01L21/223
CPC分类号： H01L29/866 , H01L21/265 , Y10S438/983
摘要： A new process making it possible to produce stable buried Zener diodes in large-sized wafers where slow ramping of diffusion temperatures is required to avoid crystal damage and other adverse effects. The process includes an initial deep ion implantation of p type dopant (boron). A second ion implantation of n type dopant (arsenic) is made over the p type implantation. Both implantations are driven in to the required degree. An additional p type dopant diffusion is made coincident with the base formation by ion implantation to establish connection to the original deep p-doped region, and an additional n type dopant diffusion is made coincident with the emitter formation to establish connection with the n type dopant implantation.
摘要翻译：一种新的工艺使得可以在大尺寸晶片中生产稳定的内置齐纳二极管，其中需要缓慢的扩散温度梯度以避免晶体损坏和其他不利影响。该方法包括p型掺杂剂（硼）的初始深离子注入。在p型注入上进行n型掺杂剂（砷）的第二离子注入。两种植入都被驱动到所需的程度。通过离子注入使另外的p型掺杂剂扩散与基底形成一致，以建立与原始深p掺杂区的连接，并且使附加的n型掺杂剂扩散与发射极形成一致以建立与n型掺杂物的连接植入。

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