会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 5. 发明申请
    • Integrated circuit with depletion mode JFET
    • 具有耗尽型JFET的集成电路
    • US20070069250A1
    • 2007-03-29
    • US11237095
    • 2005-09-28
    • Alan ChenDaniel DolanDavid KellyDaniel KerrStephen Kuehne
    • Alan ChenDaniel DolanDavid KellyDaniel KerrStephen Kuehne
    • H01L29/80
    • H01L29/808H01L21/823892H01L27/0922H01L27/098H01L29/1066H01L29/7833
    • An integrated circuit having an n-channel MOSFET device and a JFET device. The integrated circuit includes a semiconductor layer having an upper surface, an MOS transistor device formed in a doped well of a first conductivity type extending from the semiconductor upper surface and a JFET device. The JFET device includes a channel region in the semiconductor layer spaced from, and having a peak concentration positioned a predetermined distance below, the upper surface. An associated method of manufacturing includes introducing p-type dopant into the semiconductor surface to form a p-well in which the NMOS device is formed and a source and a drain of the JFET device. N-type dopant is introduced into the semiconductor surface to form an n-type region of the NMOS device below the p-well and a gate region of the JFET device. P-type dopant is introduced into the semiconductor layer to simultaneously form a higher concentration p-type region in the p-well of the NMOS device and a channel region extending between the source and drain of the JFET.
    • 具有n沟道MOSFET器件和JFET器件的集成电路。 集成电路包括具有上表面的半导体层,形成在从半导体上表面延伸的第一导电类型的掺杂阱中的MOS晶体管器件和JFET器件。 JFET器件包括半导体层中的与上表面间隔开并具有位于预定距离的峰值浓度的沟道区域。 相关联的制造方法包括将p型掺杂剂引入半导体表面以形成其中形成NMOS器件的p阱以及JFET器件的源极和漏极。 N型掺杂剂被引入到半导体表面中以在p阱的下面形成NMOS器件的n型区域和JFET器件的栅极区域。 P型掺杂剂被引入到半导体层中,以在NMOS器件的p阱和在JFET的源极和漏极之间延伸的沟道区域中同时形成更高浓度的p型区域。