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    • 2. 发明授权
    • Method and apparatus for support of multiple memory devices in a single memory socket architecture
    • 用于在单个存储器套接字架构中支持多个存储器件的方法和装置
    • US06229727B1
    • 2001-05-08
    • US09162644
    • 1998-09-28
    • Stephen J. Doyle
    • Stephen J. Doyle
    • G11C506
    • G11C8/00
    • An apparatus and method for supporting multiple configurations/sizes of random access memory devices in a single socket architecture is provided. In general, the address lines of the microprocessor are interconnected through a multiplexer and buffer arrangement that divides the address lines into two groups. The two groups of address bits, so divided, are selectively routed to predetermined pin connections of a dual in-line memory module (DIMM) socket that interconnect with predetermined address lines of the resident random access memory. The address bits are transmitted to the pin connections during each of the row address cycle and the column address cycle of the memory. The interconnections between the multiplexer/buffer and the random access memory are arranged so that a variety of standardized address pin configurations are supported by the same socket.
    • 提供了一种用于在单个套接字架构中支持多个配置/大小的随机存取存储器件的装置和方法。 通常,微处理器的地址线通过将地址线分成两组的多路复用器和缓冲器布置来互连。 两组分配的地址位被选择性地路由到与驻留随机存取存储器的预定地址线互连的双列直插存储器模块(DIMM)插座的预定引脚连接。 地址位在存储器的行地址周期和列地址周期的每一个期间被发送到引脚连接。 多路复用器/缓冲器和随机存取存储器之间的互连被布置成使得各种标准化的地址引脚配置由相同的插座支持。
    • 3. 发明授权
    • Method and apparatus for support of multiple memory types in a single
memory socket architecture
    • 用于在单个存储器套接字架构中支持多种存储器类型的方法和装置
    • US5982655A
    • 1999-11-09
    • US163154
    • 1998-09-29
    • Stephen J. Doyle
    • Stephen J. Doyle
    • G11C5/04G11C5/06
    • G11C5/04
    • An apparatus and method for supporting multiple types and configurations of random access memory devices in a single dual in line memory module (DIMM) socket architecture is provided. Typically, this architecture allows a user to select either SDRAM or EDO to be located in the socket(s) without substantially altering the connectivity between circuit components. A switching arrangement, that can be either active switches or fixed circuit traces, is used to selectively interconnect various control and addressing functions inherent in the microprocessor to appropriate pins of the memory device socket(s) depending upon whether EDO or SDRAM is used. In general, the address lines of the microprocessor are interconnected through a multiplexer and buffer arrangement that divides the address lines into two groups. The address bits are transmitted to the pin connections during each of the row address cycle and the column address cycle of the memory. The interconnections between the multiplexer/buffer and the random access memory are arranged so that a variety of standardized address pin configurations are supported by the same socket.
    • 提供了一种用于在单个双列直插存储器模块(DIMM)插座架构中支持多种类型和配置的随机存取存储器件的装置和方法。 通常,该架构允许用户选择SDRAM或EDO来定位在插座中,而基本上不改变电路组件之间的连接性。 根据是否使用EDO或SDRAM,可以使用可以是有源开关或固定电路迹线的开关装置来选择性地将微处理器固有的各种控制和寻址功能互连到存储器件插座的适当引脚。 通常,微处理器的地址线通过将地址线分成两组的多路复用器和缓冲器布置来互连。 地址位在存储器的行地址周期和列地址周期的每一个期间被发送到引脚连接。 多路复用器/缓冲器和随机存取存储器之间的互连被布置成使得各种标准化的地址引脚配置由相同的插座支持。