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1. 发明授权

US09152509B2 Transactional memory conflict management 有权
标题翻译：事务记忆冲突管理
公开(公告)号：US09152509B2
公开(公告)日：2015-10-06
申请号：US13324011
申请日：2011-12-13
申请人： Stephan Diestelhorst , Martin Pohlack , Michael Hohmuth , David Christie , Luke Yen
发明人： Stephan Diestelhorst , Martin Pohlack , Michael Hohmuth , David Christie , Luke Yen
IPC分类号： G06F13/28 , G06F13/00 , G06F11/14 , G06F9/30 , G06F9/38 , G06F11/00 , G06F9/46 , G06F9/52
CPC分类号： G06F11/1474 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3861 , G06F9/467 , G06F9/528 , G06F11/00 , G06F2209/521
摘要： A computing device initiates a transaction, corresponding to an application, which includes operations for accessing data stored in a shared memory and buffering alterations to the data as speculative alterations to the shared memory. The computing device detects a transaction abort scenario corresponding to the transaction and notifies the application regarding the transaction abort scenario. The computing device determines whether to abort the transaction based on instructions received from the application regarding the transaction abort scenario. When the transaction is to be aborted, the computing device restores the transaction to an operation prior to accessing the data stored in the shared memory and buffering alterations to the data as speculative alterations to the shared memory. When the transaction is not to be aborted, the computing device enables the transaction to continue.
摘要翻译：计算设备启动与应用相对应的事务，其包括用于访问存储在共享存储器中的数据的操作，并且缓冲对数据的改变作为对共享存储器的推测性改变。计算设备检测与事务相对应的事务中止方案，并将该事务通知给应用程序中止事件。计算设备基于从应用程序接收的关于事务中止场景的指令来确定是否中止事务。当事务被中止时，计算设备在访问存储在共享存储器中的数据之前将事务恢复为操作，并且缓冲对数据的改变作为对共享存储器的推测性改变。当事务不被中止时，计算设备使交易能够继续。

2. 发明授权

US08943278B2 Protecting large regions without operating-system support 有权
标题翻译：保护大型区域，无需操作系统支持
公开(公告)号：US08943278B2
公开(公告)日：2015-01-27
申请号：US13563143
申请日：2012-07-31
申请人： Martin T. Pohlack , Stephan Diestelhorst
发明人： Martin T. Pohlack , Stephan Diestelhorst
IPC分类号： G06F12/00
CPC分类号： G06F12/1441
摘要： A system and method for providing very large read-sets for hardware transactional memory with limited hardware support by monitoring meta data such as page table entries. The system and method include a Hardware-based Transactional Memory (HTM) mechanism that tracks meta-data such as page-table entries (PTE) rather than all the data itself. The HTM mechanism protects large regions of memory by providing conflict detection so that regions of memory can be located within a local read or write set.
摘要翻译：一种用于通过监视元数据（如页表条目）为硬件事务存储器提供非常大的读取集的有限的硬件支持的系统和方法。该系统和方法包括基于硬件的事务存储器（HTM）机制，其跟踪元数据，例如页表条目（PTE），而不是所有数据本身。 HTM机制通过提供冲突检测来保护大内存区域，以便存储器区域可以位于本地读或写集合内。

3. 发明申请

US20130159653A1 Predictive Lock Elision 审中-公开
标题翻译：预测锁定
公开(公告)号：US20130159653A1
公开(公告)日：2013-06-20
申请号：US13331221
申请日：2011-12-20
申请人： Martin T. Pohlack , Stephan Diestelhorst
发明人： Martin T. Pohlack , Stephan Diestelhorst
IPC分类号： G06F12/14
CPC分类号： G06F9/528
摘要： In at least one embodiment, a method includes determining whether to elide a lock operation based on success of or failure of one or more previous transactional memory operations associated with one or more respective previous lock elisions. In at least one embodiment of the method, the lock operation is associated with a first access of a shared resource and the one or more previous lock elisions are associated with respective one or more previous accesses of the shared resource.
摘要翻译：在至少一个实施例中，一种方法包括基于与一个或多个相应的先前锁定精度相关联的一个或多个先前的事务性存储器操作的成功或失败来确定是否去除锁定操作。在该方法的至少一个实施例中，锁定操作与共享资源的第一次访问相关联，并且一个或多个先前锁定精灵与共享资源的相应一个或多个先前访问相关联。

4. 发明授权

US08352688B2 Preventing unintended loss of transactional data in hardware transactional memory systems 有权
公开(公告)号：US08352688B2
公开(公告)日：2013-01-08
申请号：US12946743
申请日：2010-11-15
申请人： Jaewoong Chung , David S. Christie , Michael P. Hohmuth , Stephan Diestelhorst , Martin T. Pohlack , Luke Yen
发明人： Jaewoong Chung , David S. Christie , Michael P. Hohmuth , Stephan Diestelhorst , Martin T. Pohlack , Luke Yen
IPC分类号： G06F12/00
CPC分类号： G06F12/00 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3857
摘要： A method and apparatus are disclosed for implementing early release of speculatively read data in a hardware transactional memory system. A processing core comprises a hardware transactional memory system configured to receive an early release indication for a specified word of a group of words in a read set of an active transaction. The early release indication comprises a request to remove the specified word from the read set. In response to the early release request, the processing core removes the group of words from the read set only after determining that no word in the group other than the specified word has been speculatively read during the active transaction.

5. 发明申请

US20120124563A1 COMPILER SUPPORT TECHNIQUE FOR HARDWARE TRANSACTIONAL MEMORY SYSTEMS 有权
标题翻译：硬件交互式存储系统的编译器支持技术
公开(公告)号：US20120124563A1
公开(公告)日：2012-05-17
申请号：US12947336
申请日：2010-11-16
申请人： Jaewoong Chung , Rahmet Ulya Karpuzcu , David S. Christie , Michael P. Hohmuth , Stephan Diestelhorst , Martin T. Pohlack
发明人： Jaewoong Chung , Rahmet Ulya Karpuzcu , David S. Christie , Michael P. Hohmuth , Stephan Diestelhorst , Martin T. Pohlack
IPC分类号： G06F9/45
CPC分类号： G06F8/447 , G06F9/467
摘要： A method and apparatus for compiling software written to be executed on a microprocessor that supports at least one hardware transactional memory function is provided. A compiler that supports at least one software transactional memory function is adapted to include a runtime system that maps between the at least one software transactional memory function and the at least one hardware transactional memory instruction.
摘要翻译：提供了一种用于编译写入要在支持至少一个硬件事务存储器功能的微处理器上执行的软件的方法和装置。支持至少一个软件事务性存储器功能的编译器适于包括在所述至少一个软件事务存储器功能与所述至少一个硬件事务存储器指令之间映射的运行时系统。

6. 发明申请

US20110040906A1 Multi-level Buffering of Transactional Data 有权
标题翻译：事务数据的多级缓冲
公开(公告)号：US20110040906A1
公开(公告)日：2011-02-17
申请号：US12627956
申请日：2009-11-30
申请人： Jaewoong Chung , David S. Christie , Michael P. Hohmuth , Stephan Diestelhorst , Martin Pohlack
发明人： Jaewoong Chung , David S. Christie , Michael P. Hohmuth , Stephan Diestelhorst , Martin Pohlack
IPC分类号： G06F5/14 , G06F12/00
CPC分类号： G06F5/16 , G06F9/528
摘要： An apparatus, method, and system for implementing a hardware transactional memory (HTM) system with multiple levels of transactional buffers. The apparatus comprises a data cache configured to buffer data in a shared (by a plurality of processing cores) memory accessed by speculative memory access operations and to retain the data during at least a portion of an attempt to execute the atomic memory transaction. The apparatus also comprises an overflow detection circuit configured to detect an overflow condition upon determining that the data cache has insufficient capacity to buffer a portion of data accessed as part of the atomic memory transaction, as well as a buffering circuit configured to respond to the detection of the overflow condition by preventing the portion of data from being buffered in the data cache and buffering the portion of data in a secondary buffer separate from the data cache.
摘要翻译：一种用于实现具有多级事务缓冲器的硬件事务存储器（HTM）系统的装置，方法和系统。该装置包括数据高速缓存，其被配置为缓冲由推测性存储器访问操作访问的共享（多个处理核心）存储器中的数据，并且在至少一部分尝试期间保留数据以执行原子存储器事务。该装置还包括：溢出检测电路，其被配置为在确定数据高速缓冲存储器不足以缓冲作为原子存储器事务的一部分访问的数据的一部分时检测溢出状况，以及配置为响应于检测的缓冲电路通过防止数据部分被缓冲在数据高速缓冲存储器中并缓冲与数据高速缓存分开的辅助缓冲器中的数据的部分，来实现溢出状态。

7. 发明授权

US08739164B2 Automatic suspend atomic hardware transactional memory in response to detecting an implicit suspend condition and resume thereof 有权
标题翻译：响应于检测到隐式暂停条件并恢复原状硬件事务内存，自动挂起
公开(公告)号：US08739164B2
公开(公告)日：2014-05-27
申请号：US12711851
申请日：2010-02-24
申请人： Jaewoong Chung , David S. Christie , Michael P. Hohmuth , Stephan Diestelhorst , Martin Pohlack
发明人： Jaewoong Chung , David S. Christie , Michael P. Hohmuth , Stephan Diestelhorst , Martin Pohlack
IPC分类号： G06F9/46 , G06F13/00 , G06F13/28
CPC分类号： G06F9/466 , G06F9/30087 , G06F9/3834
摘要： An apparatus and method is disclosed for a computer processor configured to access a memory shared by a plurality of processing cores and to execute a plurality of memory access operations in a transactional mode as a single atomic transaction and to suspend the transactional mode in response to determining an implicit suspend condition, such as a program control transfer. As part of executing the transaction, the processor marks data accessed by the speculative memory access operations as being speculative data. In response to determining a suspend condition (including by detecting a control transfer in an executing thread) the processor suspends the transactional mode of execution, which includes setting a suspend flag and suspending marking speculative data. If the processor later detects a resumption condition (e.g., a return control transfer corresponding to a return from the control transfer), the processor is configured to resume the marking of speculative data.
摘要翻译：公开了一种用于计算机处理器的设备和方法，该计算机处理器被配置为访问由多个处理核心共享的存储器，并且以事务模式执行多个存储器访问操作作为单个原子事务，并响应确定事件来暂停事务模式一个隐式挂起条件，如程序控制转移。作为执行事务的一部分，处理器将通过推测存储器访问操作访问的数据标记为推测数据。响应于确定暂停条件（包括通过检测执行线程中的控制传输），处理器暂停执行的事务模式，其包括设置挂起标志和暂停标记推测数据。如果处理器稍后检测到恢复条件（例如，对应于来自控制传输的返回的返回控制传送），则处理器被配置为恢复对推测数据的标记。

8. 发明申请

US20120233411A1 Protecting Large Objects Within an Advanced Synchronization Facility 有权
标题翻译：保护高级同步工具中的大对象
公开(公告)号：US20120233411A1
公开(公告)日：2012-09-13
申请号：US13041867
申请日：2011-03-07
申请人： Martin T. Pohlack , Michael P. Hohmuth , Stephan Diestelhorst , David S. Christie , Jaewoong Chung
发明人： Martin T. Pohlack , Michael P. Hohmuth , Stephan Diestelhorst , David S. Christie , Jaewoong Chung
IPC分类号： G06F12/00
CPC分类号： G06F12/1072 , G06F9/3004 , G06F9/30087 , G06F9/467 , G06F12/0815 , G06F12/1027
摘要： A system and method are disclosed for allowing protection of larger areas than memory lines by monitoring accessed and dirty bits in page tables. More specifically, in some embodiments, a second associative structure with a different granularity is provided to filter out a large percentage of false positives. By providing the associative structure with sufficient size, the structure exactly specifies a region in which conflicting cache lines lie. If entries within this region are evicted from the structure, enabling the tracking for the entire index filters out a substantial number of false positives (depending on a granularity and a number of indices present). In some embodiments, this associative structure is similar to a translation look aside buffer (TLB) with 4 k, 2M entries.
摘要翻译：公开了一种系统和方法，用于通过监视页表中的访问和脏位来允许保护比存储线更大的区域。更具体地，在一些实施例中，提供具有不同粒度的第二关联结构以过滤大量的误报。通过提供具有足够大小的关联结构，该结构精确地指定了冲突的高速缓存行所在的区域。如果该区域内的条目被从结构中逐出，则使整个索引的跟踪能够滤除大量的假阳性（取决于存在的粒度和数量）。在一些实施例中，该关联结构类似于具有4k，2M条目的翻译旁边缓冲器（TLB）。

9. 发明授权

US08127057B2 Multi-level buffering of transactional data 有权
标题翻译：事务数据的多级缓冲
公开(公告)号：US08127057B2
公开(公告)日：2012-02-28
申请号：US12627956
申请日：2009-11-30
申请人： Jaewoong Chung , David S. Christie , Michael P. Hohmuth , Stephan Diestelhorst , Martin Pohlack
发明人： Jaewoong Chung , David S. Christie , Michael P. Hohmuth , Stephan Diestelhorst , Martin Pohlack
IPC分类号： G06F13/12
CPC分类号： G06F5/16 , G06F9/528
摘要： An apparatus, method, and system for implementing a hardware transactional memory (HTM) system with multiple levels of transactional buffers. The apparatus comprises a data cache configured to buffer data in a shared (by a plurality of processing cores) memory accessed by speculative memory access operations and to retain the data during at least a portion of an attempt to execute the atomic memory transaction. The apparatus also comprises an overflow detection circuit configured to detect an overflow condition upon determining that the data cache has insufficient capacity to buffer a portion of data accessed as part of the atomic memory transaction, as well as a buffering circuit configured to respond to the detection of the overflow condition by preventing the portion of data from being buffered in the data cache and buffering the portion of data in a secondary buffer separate from the data cache.
摘要翻译：一种用于实现具有多级事务缓冲器的硬件事务存储器（HTM）系统的装置，方法和系统。该装置包括数据高速缓存，其被配置为缓冲由推测性存储器访问操作访问的共享（多个处理核心）存储器中的数据，并且在至少一部分尝试期间保留数据以执行原子存储器事务。该装置还包括：溢出检测电路，其被配置为在确定数据高速缓冲存储器不足以缓冲作为原子存储器事务的一部分访问的数据的一部分时检测溢出状况，以及配置为响应于检测的缓冲电路通过防止数据部分被缓冲在数据高速缓冲存储器中并缓冲与数据高速缓存分开的辅助缓冲器中的数据的部分，来实现溢出状态。

10. 发明申请

US20110307689A1 PROCESSOR SUPPORT FOR HARDWARE TRANSACTIONAL MEMORY 有权
标题翻译：硬件交易存储器的处理器支持
公开(公告)号：US20110307689A1
公开(公告)日：2011-12-15
申请号：US12814025
申请日：2010-06-11
申请人： Jaewoong Chung , David S. Christie , Michael P. Hohmuth , Stephan Diestelhorst , Martin T. Pohlack , Luke Yen
发明人： Jaewoong Chung , David S. Christie , Michael P. Hohmuth , Stephan Diestelhorst , Martin T. Pohlack , Luke Yen
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3842 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3857 , G06F9/3859 , G06F9/467
摘要： A processing core of a plurality of processing cores is configured to execute a speculative region of code as a single atomic memory transaction with respect one or more others of the plurality of processing cores. In response to determining an abort condition for an issued one of the plurality of program instructions and in response to determining that the issued program instruction is not part of a mispredicted execution path, the processing core is configured to abort an attempt to execute the speculative region of code.
摘要翻译：多个处理核心的处理核心被配置为相对于多个处理核心中的一个或多个处理核心执行代码的推测区域作为单个原子存储器事务处理。响应于确定所述多个程序指令中的已发出的程序指令的中止条件，并且响应于确定所发出的程序指令不是错误预测的执行路径的一部分，所述处理核心被配置为中止尝试执行所述推测区域的代码。

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