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    • 1. 发明申请
    • Energy Efficient Processor Having Heterogeneous Cache
    • 具有异构缓存的节能处理器
    • US20130094318A1
    • 2013-04-18
    • US13271771
    • 2011-10-12
    • Nam Sung KimStark C. Draper
    • Nam Sung KimStark C. Draper
    • G11C5/14
    • G06F12/0864G06F11/1064G06F2212/1028Y02D10/13
    • A heterogeneous cache structure provides several memory cells into different ways each associated with different minimum voltages below which the memory cells produce substantial state errors. Reduced voltage operation of the cache may be accompanied by deactivating different ways according to the voltage reduction. The differentiation between the memory cells in the ways may be implemented by devoting different amounts of integrated circuit area to each memory cell either by changing the size of the transistors comprising the memory cell or devoting additional transistors to each memory cell in the form of shared error correcting codes or backup memory cells.
    • 异构缓存结构提供多个不同方式的多个存储器单元,每个存储单元与不同的最小电压相关联,低于该最小电压时,存储器单元产生实质的状态误差。 缓存的降压操作可伴随着根据电压降低而不同的方式停用。 存储器单元之间的区别可以通过将不同量的集成电路区域投入到每个存储器单元来实现,方法是通过改变包括存储器单元的晶体管的尺寸或者以共享误差的形式将额外的晶体管用于每个存储器单元 更正代码或备份存储单元。
    • 4. 发明授权
    • Maximum likelihood decoding via mixed-integer adaptive linear programming
    • 通过混合整数自适应线性规划的最大似然解码
    • US07945845B2
    • 2011-05-17
    • US11764938
    • 2007-06-19
    • Stark C. DraperJonathan S. Yedidia
    • Stark C. DraperJonathan S. Yedidia
    • H03M13/03
    • H03M13/1105H03M13/37H03M13/451H03M13/458
    • A method and system decode a sequence of symbols received via a channel to a codeword of an error-correcting code. Log-likelihood ratios are determined from a sequence of symbols received via a channel. A set of constraints is initialized according to the log-likelihood ratios. An adaptive linear programming decoder is applied to the set of constraints and the log- likelihood ratios according to an error-correcting code to produce an estimate of the codeword and an updated set of constraints. If the estimate of the codeword is a non-integer pseudo codeword, further update the set of updated constraints with a set of integer constraints if the estimate of the codeword is the non-integer pseudo codeword, and proceeding with the applying step, and otherwise producing the estimate of the codeword as the final codeword.
    • 方法和系统将经由信道接收的符号序列解码为纠错码的码字。 从通过信道接收的符号序列确定对数似然比。 根据对数似然比初始化一组约束。 根据纠错码将自适应线性规划解码器应用于约束集和对数似然比,以产生码字的估计和更新的约束集合。 如果码字的估计是非整数伪码字,则如果码字的估计是非整数伪码字,并进行应用步骤,则用一组整数约束进一步更新更新的约束集合,否则 产生码字的估计作为最终码字。
    • 8. 发明授权
    • Pre-processing biometric parameters before encoding and decoding
    • 在编码和解码之前预处理生物特征参数
    • US08375218B2
    • 2013-02-12
    • US11928687
    • 2007-10-30
    • Jonathan S. YedidiaStark C. DraperYagiz SutcuAnthony Vetro
    • Jonathan S. YedidiaStark C. DraperYagiz SutcuAnthony Vetro
    • G06F21/00
    • H04L9/3236G06K9/00073G06K9/0061H04L9/3231H04L2209/30H04L2209/805
    • Biometric parameters acquired from human faces, voices, fingerprints, and irises are used for user authentication and access control. Because the biometric parameters are continuous and vary from one reading to the next, syndrome codes are applied to determine biometric syndrome vectors. The biometric syndrome vectors can be stored securely, while tolerating an inherent variability of biometric data. The stored biometric syndrome vector is decoded during user authentication using biometric parameters acquired at that time. The syndrome codes can also be used to encrypt and decrypt data. The biometric parameters can be pre-processed to form a binary representation, in which the binary representation has a set of predetermined statistical properties enforced imposed by a set of binary logical conditions.
    • 从人脸,语音,指纹和虹膜获取的生物特征参数用于用户认证和访问控制。 因为生物特征参数是连续的,并且从一个读数到下一个读数不同,所以应用校正子码来确定生物统计学综合征矢量。 可以安全地存储生物特征综合征矢量,同时容忍生物特征数据的固有变异性。 存储的生物统计量子载体在用户认证期间使用当时获取的生物特征参数进行解码。 校正码也可用于加密和解密数据。 生物特征参数可以被预处理以形成二进制表示,其中二进制表示具有由一组二进制逻辑条件强加的一组预定的统计特性。
    • 9. 发明申请
    • Method and System for Compound Conditional Source Coding
    • 复合条件源编码方法与系统
    • US20080279281A1
    • 2008-11-13
    • US11745519
    • 2007-05-08
    • Stark C. DraperEmin Martinian
    • Stark C. DraperEmin Martinian
    • H04B1/66
    • H03M7/30
    • Embodiments of the invention describe a compound conditional source coding method and system for communicating source data over a network. Length-n random uncompressed source data are drawn according to a distribution px(x), and serves as input data to an encoder. A set P of candidate side-information vectors is also input to the encoder. The encoder encodes the source data, utilizing the set of the candidate side-information vectors, to produce an encoded message. The message is transmitted to a decoder. The decoder decodes the received message to produce a source estimate, using selected side-information vector and an index of the selected side-information vector in the set of the candidate side-information vectors.
    • 本发明的实施例描述了一种用于通过网络传送源数据的复合条件源编码方法和系统。 长度为n的随机未压缩源数据根据分布p x x(x)绘制,并且用作编码器的输入数据。 候选侧信息向量的集合P也被输入到编码器。 编码器利用候选侧信息向量集合对源数据进行编码,以产生编码消息。 该消息被发送到解码器。 解码器对所接收的消息进行解码以使用候选侧信息向量的集合中的所选侧信息向量和所选择的侧信息向量的索引来产生源估计。
    • 10. 发明授权
    • Energy efficient processor having heterogeneous cache
    • 具有异构缓存的节能处理器
    • US08687453B2
    • 2014-04-01
    • US13271771
    • 2011-10-12
    • Nam Sung KimStark C. Draper
    • Nam Sung KimStark C. Draper
    • G11C5/14
    • G06F12/0864G06F11/1064G06F2212/1028Y02D10/13
    • A heterogeneous cache structure provides several memory cells into different ways each associated with different minimum voltages below which the memory cells produce substantial state errors. Reduced voltage operation of the cache may be accompanied by deactivating different ways according to the voltage reduction. The differentiation between the memory cells in the ways may be implemented by devoting different amounts of integrated circuit area to each memory cell either by changing the size of the transistors comprising the memory cell or devoting additional transistors to each memory cell in the form of shared error correcting codes or backup memory cells.
    • 异构缓存结构提供多个不同方式的多个存储器单元,每个存储单元与不同的最小电压相关联,低于该最小电压时,存储器单元 缓存的降压操作可伴随着根据电压降低而不同的方式停用。 存储器单元之间的区别可以通过将不同量的集成电路区域投入到每个存储器单元来实现,方法是通过改变包括存储器单元的晶体管的尺寸或者以共享误差的形式将额外的晶体管用于每个存储器单元 更正代码或备份存储单元。