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1. 发明申请

US20090283817A1 FLOATING GATE STRUCTURES 有权
标题翻译：浮动门结构
公开(公告)号：US20090283817A1
公开(公告)日：2009-11-19
申请号：US12165272
申请日：2008-06-30
申请人： Tejas Krishnamohan , Krishna Parat , Kyu Min , Srivardhan Gowda , Thomas M. Graettinger , Nirmal Ramaswamy
发明人： Tejas Krishnamohan , Krishna Parat , Kyu Min , Srivardhan Gowda , Thomas M. Graettinger , Nirmal Ramaswamy
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： H01L21/28052 , H01L21/28273 , H01L29/66825 , H01L29/7881
摘要： Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the semiconductor substrate, and a floating gate structure comprising at least a first region having a first electron energy level or electron workfunction or carrier capture efficiency coupled with the tunnel dielectric and a second region having a second electron energy level or electron workfunction or carrier capture efficiency coupled with the first region wherein the first electron energy level or electron workfunction or carrier capture efficiency is less than the second electron energy level or electron workfunction or carrier capture efficiency. Such electronic device may reduce the thickness of the floating gate structure or reduce leakage current through an inter-gate dielectric, or combinations thereof, compared with a floating gate structure that comprises only polysilicon.
摘要翻译：通常描述浮栅结构。在一个示例中，电子设备包括半导体衬底，与半导体衬底耦合的隧道电介质，以及浮栅结构，其至少包括具有第一电子能级或电子功函数的第一区域或与隧道电介质耦合的载流子捕获效率以及第二区域，其具有与第一区域耦合的第二电子能级或电子功能函数或载流子捕获效率，其中第一电子能级或电子功函数或载流子捕获效率小于第二电子能级或电子功函数或载流子俘获效率。与仅包含多晶硅的浮动栅极结构相比，这种电子器件可以减小浮置栅极结构的厚度或减小通过栅极间电介质或其组合的泄漏电流。

2. 发明授权

US06958485B2 Hybrid molecular memory devices and methods of use thereof 失效
标题翻译：混合分子记忆装置及其使用方法
公开(公告)号：US06958485B2
公开(公告)日：2005-10-25
申请号：US10729144
申请日：2003-12-05
申请人： Veena Misra , Srivardhan Gowda , Guru Mathur
发明人： Veena Misra , Srivardhan Gowda , Guru Mathur
IPC分类号： G11C13/02 , H01L51/00 , H01L51/30 , H01L29/06
CPC分类号： G11C13/0014 , B82Y10/00 , G11C13/0009 , G11C2213/15 , H01L27/285 , H01L51/0077 , H01L51/0595
摘要： The present invention provides hybrid microelectronic memory device, comprising: (a) a substrate having a surface, a first region of first work function adjacent the surface, and a second region of second work function adjacent the surface and adjacent the first region; (b) a film comprising redox-active molecules on the first and second regions; and (c) an electrode connected to the film. The present invention further provides a hybrid microelectronic memory device, comprising: (a) a substrate having surface and a structure or region such as a diode for increasing the retention time of the device formed adjacent the surface; (b) a film comprising redox-active molecules on or associated with the region or structure; and (c) an electrode connected to the redox active molecules opposite the substrate surface. Methods of using such devices are also described.
摘要翻译：本发明提供了一种混合式微电子存储装置，包括：（a）具有表面，邻近表面的第一功函数的第一区域和与表面相邻并邻近第一区域的第二功能函数的第二区域的衬底; （b）在第一和第二区域上包含氧化还原活性分子的膜; 和（c）连接到膜的电极。本发明还提供了一种混合微电子存储器件，包括：（a）具有表面和诸如二极管的结构或区域的衬底的衬底，用于增加邻近表面形成的器件的保留时间; （b）在该区域或结构上或与该区域或结构相关联的包含氧化还原活性分子的膜; 和（c）连接到与衬底表面相对的氧化还原活性分子的电极。还描述了使用这种装置的方法。

3. 发明申请

US20110147827A1 Flash memory with partially removed blocking dielectric in the wordline direction 审中-公开
标题翻译：在字线方向上部分去除阻塞电介质的闪存
公开(公告)号：US20110147827A1
公开(公告)日：2011-06-23
申请号：US12655090
申请日：2009-12-23
申请人： Fatma Arzum Simsek-Ege , Sanh Tang , Nirmal Ramaswamy , Thomas M. Graettinger , Kyu S. Min , Tejas Krishnamohan , Srivardhan Gowda
发明人： Fatma Arzum Simsek-Ege , Sanh Tang , Nirmal Ramaswamy , Thomas M. Graettinger , Kyu S. Min , Tejas Krishnamohan , Srivardhan Gowda
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L29/40117 , H01L29/792
摘要： The present disclosure relates generally to the fabrication of non-volatile memory. In at least one embodiment, the present disclosure relates to forming a layered blocking dielectric which has a portion thereof removed in the wordline direction.
摘要翻译：本公开一般涉及非易失性存储器的制造。在至少一个实施例中，本公开涉及形成分层阻挡电介质，其具有沿字线方向的一部分。

4. 发明申请

US20050121660A1 Hybrid molecular memory devices and methods of use thereof 失效
公开(公告)号：US20050121660A1
公开(公告)日：2005-06-09
申请号：US10729144
申请日：2003-12-05
申请人： Veena Misra , Srivardhan Gowda , Guru Mathur
发明人： Veena Misra , Srivardhan Gowda , Guru Mathur
IPC分类号： G11C13/02 , H01L51/00 , H01L51/30 , H01L29/06
CPC分类号： G11C13/0014 , B82Y10/00 , G11C13/0009 , G11C2213/15 , H01L27/285 , H01L51/0077 , H01L51/0595
摘要： The present invention provides hybrid microelectronic memory device, comprising: (a) a substrate having a surface, a first region of first work function adjacent the surface, and a second region of second work function adjacent the surface and adjacent the first region; (b) a film comprising redox-active molecules on the first and second regions; and (c) an electrode connected to the film. The present invention further provides a hybrid microelectronic memory device, comprising: (a) a substrate having surface and a structure or region such as a diode for increasing the retention time of the device formed adjacent the surface; (b) a film comprising redox-active molecules on or associated with the region or structure; and (c) an electrode connected to the redox active molecules opposite the substrate surface. Methods of using such devices are also described.

5. 发明申请

US20190043960A1 MODIFIED FLOATING GATE AND DIELECTRIC LAYER GEOMETRY IN 3D MEMORY ARRAYS 审中-公开
公开(公告)号：US20190043960A1
公开(公告)日：2019-02-07
申请号：US16022540
申请日：2018-06-28
申请人： Randy Koval , Srikant Jayanti , Hiroyuki Sanda , Meng-Wei Kuo , Srivardhan Gowda , Krishna Parat
发明人： Randy Koval , Srikant Jayanti , Hiroyuki Sanda , Meng-Wei Kuo , Srivardhan Gowda , Krishna Parat
IPC分类号： H01L29/423 , H01L27/11556 , H01L27/11521 , H01L29/06 , H01L29/10 , H01L29/04 , H01L21/28 , H01L21/311 , H01L21/3213 , H01L21/02
摘要： A 3D memory structure including a modified floating gate and dielectric layer geometry is described. In embodiments, a memory cell includes a channel region and a floating gate where a length of the floating gate along a direction of the channel region is substantially longer than a length of the floating gate along an orthogonal direction along the channel region. A control gate adjacent to the floating gate extends at least as long as the control gate along the direction of the channel region and includes a tapered edge extending away from the channel region towards the control gate. In embodiments, a dielectric layer between the control gate and the floating gate may follow the tapered edge along the floating gate and form a discrete region proximate to the floating gate to at least partially insulate the floating gate from an adjacent memory cell. Other embodiments are disclosed and claimed.

6. 发明授权

US07989289B2 Floating gate structures 有权
标题翻译：浮门结构
公开(公告)号：US07989289B2
公开(公告)日：2011-08-02
申请号：US12165272
申请日：2008-06-30
申请人： Tejas Krishnamohan , Krishna Parat , Kyu Min , Srivardhan Gowda , Thomas M. Graettinger , Nirmal Ramaswamy
发明人： Tejas Krishnamohan , Krishna Parat , Kyu Min , Srivardhan Gowda , Thomas M. Graettinger , Nirmal Ramaswamy
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L21/28052 , H01L21/28273 , H01L29/66825 , H01L29/7881
摘要： Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the semiconductor substrate, and a floating gate structure comprising at least a first region having a first electron energy level or electron workfunction or carrier capture efficiency coupled with the tunnel dielectric and a second region having a second electron energy level or electron workfunction or carrier capture efficiency coupled with the first region wherein the first electron energy level or electron workfunction or carrier capture efficiency is less than the second electron energy level or electron workfunction or carrier capture efficiency. Such electronic device may reduce the thickness of the floating gate structure or reduce leakage current through an inter-gate dielectric, or combinations thereof, compared with a floating gate structure that comprises only polysilicon.
摘要翻译：通常描述浮栅结构。在一个示例中，电子设备包括半导体衬底，与半导体衬底耦合的隧道电介质，以及浮栅结构，其至少包括具有第一电子能级或电子功函数的第一区域或与隧道电介质耦合的载流子捕获效率以及第二区域，其具有与第一区域耦合的第二电子能级或电子功能函数或载流子捕获效率，其中第一电子能级或电子功函数或载流子捕获效率小于第二电子能级或电子功函数或载流子俘获效率。与仅包含多晶硅的浮动栅极结构相比，这种电子器件可以减小浮置栅极结构的厚度或减小通过栅极间电介质或其组合的泄漏电流。

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