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1. 发明授权

US06753133B2 Method and manufacturing a semiconductor device having a ruthenium or a ruthenium oxide 失效
标题翻译：方法和制造具有钌或氧化钌的半导体器件
公开(公告)号：US06753133B2
公开(公告)日：2004-06-22
申请号：US10091531
申请日：2002-03-07
申请人： Yasuhiro Ono , Sota Shinohara
发明人： Yasuhiro Ono , Sota Shinohara
IPC分类号： G03F742
CPC分类号： G03F7/427 , H01L21/31138 , H01L21/31144 , H01L21/76802
摘要： A method for fabricating a semiconductor device includes the following steps. At first, a Ru or RuO2 film and a SiO2 layer are formed over a Si substrate in that order. Then, a resist pattern is formed on the SiO2 layer and is then provided as a mask to etch the SiO2 layer to form a contact hole. The Ru or RuO2 film is exposed at the bottom of the contact hole. Subsequently, a plasma ashing is performed using an ashing gas prepared by mixing O2 with N2 where the composition ratio of N2 is 50% or more at a substrate temperature of 200° C. or more for ashing the resist pattern. Consequently, the present invention allows the ashing of the resist pattern over the Ru or RuO2 film at a high selectivity to prevent the Ru or RuO2 film from becoming disappeared.
摘要翻译：一种制造半导体器件的方法包括以下步骤。首先，在Si基板上依次形成Ru或RuO 2膜和SiO 2层。然后，在SiO 2层上形成抗蚀剂图案，然后提供作为掩模以蚀刻SiO 2层以形成接触孔。 Ru或RuO2膜暴露在接触孔的底部。随后，使用通过混合O 2和N 2制备的灰化气体进行等离子体灰化，其中在200℃或更高的衬底温度下，N2的组成比为50％或更高，用于灰化抗蚀剂图案。因此，本发明允许以高选择性使抗蚀剂图案在Ru或RuO 2膜上灰化以防止Ru或RuO 2膜消失。

2. 发明授权

US5990508A Ferroelectric memory 失效
标题翻译：铁电存储器
公开(公告)号：US5990508A
公开(公告)日：1999-11-23
申请号：US95055
申请日：1998-06-10
申请人： Sota Shinohara
发明人： Sota Shinohara
IPC分类号： H01L21/8247 , H01L21/02 , H01L21/768 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/72
CPC分类号： H01L27/11502 , H01L21/76877 , H01L21/76895 , H01L27/10852 , H01L27/11507 , H01L28/60
摘要： A contact hole is formed in a protective film 9 so as to communicate with an upper electrode 15. In the contact hole is formed a conductor 13 made of substantially the same material as used for the upper electrode 15, so as to communicate with the upper electrode 15 and extend to the outside of the contact hole. The conductor 13 is electrically connected to a memory cell transistor, by a wiring layer 14.
摘要翻译：在保护膜9中形成接触孔，以与上电极15连通。在接触孔中形成导体13，导体13由与上电极15相同的材料制成，以与上电极15连通。电极15并延伸到接触孔的外部。导体13通过布线层14与存储单元晶体管电连接。

3. 发明授权

US06887752B2 Semiconductor memory and process for fabricating the same 失效
标题翻译：半导体存储器及其制造方法
公开(公告)号：US06887752B2
公开(公告)日：2005-05-03
申请号：US10690316
申请日：2003-10-21
申请人： Sota Shinohara , Koichi Takemura , Yasuhiro Tsujita , Hidemitsu Mori
发明人： Sota Shinohara , Koichi Takemura , Yasuhiro Tsujita , Hidemitsu Mori
IPC分类号： H01L21/28 , H01L21/02 , H01L21/8242 , H01L21/8246 , H01L27/105 , H01L27/108 , H01L27/115
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/75
摘要： In a semiconductor memory, a barrier layer formed of a first metal film, a metal nitride film and a second metal film laminated in the named order is formed under a lower electrode of a ferroelectric capacitor in a memory cell, in order to minimize a pealing and lifting of the lower electrode from an underlying plug in the process of forming a ferroelectric material film as a capacitor dielectric film and in its succeeding annealing process. The metal nitride film is formed of a nitride of a metal constituting the first or second metal film.
摘要翻译：在半导体存储器中，在存储单元中的强电介质电容器的下部电极的下方形成由第一金属膜，金属氮化物膜和第二金属膜形成的阻挡层，以便将其剥离并且在形成作为电容器电介质膜的铁电材料膜的过程中以及在其后续的退火工艺中，从下面的电极提升下电极。金属氮化物膜由构成第一或第二金属膜的金属的氮化物形成。

4. 发明授权

US06281536B1 Ferroelectric memory device with improved ferroelectric capacity characteristic 有权
标题翻译：具有改进的铁电容量特性的铁电存储器件
公开(公告)号：US06281536B1
公开(公告)日：2001-08-28
申请号：US09287413
申请日：1999-04-07
申请人： Sota Shinohara , Kazushi Amanuma , Yukinobu Murao , Yuukoh Katoh , Tsuneo Takeuchi , Yoshihiro Hayashi
发明人： Sota Shinohara , Kazushi Amanuma , Yukinobu Murao , Yuukoh Katoh , Tsuneo Takeuchi , Yoshihiro Hayashi
IPC分类号： H01L2972
CPC分类号： H01L27/11502 , H01L28/55
摘要： A ferroelectric memory device includes a ferroelectric capacitance element formed through an insulating film on a semiconductor substrate. The ferroelectric capacitance element includes a lower electrode, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film. The upper electrode has a laminate structure which contains a conductive oxide layer of first metal which is connected with the ferroelectric film.
摘要翻译：铁电存储器件包括通过半导体衬底上的绝缘膜形成的铁电电容元件。铁电电容元件包括下电极，形成在下电极上的铁电膜和形成在铁电体膜上的上电极。上部电极具有包含与铁电体膜连接的第一金属的导电性氧化物层的层叠结构。

5. 发明授权

US06730955B2 Semiconductor memory and process for fabricating the same 失效
公开(公告)号：US06730955B2
公开(公告)日：2004-05-04
申请号：US10100336
申请日：2002-03-18
申请人： Sota Shinohara , Koichi Takemura , Yasuhiro Tsujita , Hidemitsu Mori
发明人： Sota Shinohara , Koichi Takemura , Yasuhiro Tsujita , Hidemitsu Mori
IPC分类号： H01L2968
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/75
摘要： In a semiconductor memory, a barrier layer formed of a first metal film, a metal nitride film and a second metal film laminated in the named order is formed under a lower electrode of a ferroelectric capacitor in a memory cell, in order to minimize a pealing and lifting of the lower electrode from an underlying plug in the process of forming a ferroelectric material film as a capacitor dielectric film and in its succeeding annealing process. The metal nitride film is formed of a nitride of a metal constituting the first or second metal film.

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