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1. 发明专利

JP2010251771A Composite laminated chip element 有权
标题翻译：复合层压片元件
公开(公告)号：JP2010251771A
公开(公告)日：2010-11-04
申请号：JP2010126211
申请日：2010-06-01
申请人： Soon-Ha Hwang , Innochips Technology Co Ltd , Duk-Hee Kim , In-Kil Park , イノチップス・テクノロジー・カンパニー・リミテッド , ドク−ヒキム , イン−キルパク , スン−ハファン
发明人： PARK IN-KIL , HWANG SOON-HA , KIM DUK-HEE
IPC分类号： H01G4/40 , H01C1/148 , H01C7/00 , H01C7/02 , H01C7/04 , H01C7/10 , H01C7/18 , H01C13/02 , H01F17/00 , H01F27/00 , H01G4/232 , H01L27/02
CPC分类号： H01G4/40 , H01C1/148 , H01C7/008 , H01C7/18 , H01C13/02 , H01F17/0006 , H01F27/40 , H01F2017/0026 , H01G4/232 , H01G4/35 , H03H1/02 , H03H2001/0014 , H03H2001/0085 , H03H2001/0092
摘要： PROBLEM TO BE SOLVED: To provide a laminated chip element of which the frequency characteristics, such as noise elimination and insertion loss, are enhanced. SOLUTION: This laminated chip element includes a first sheet of at least one sheet of a plurality of sheets continuously formed so that a first and a second conductor patterns respectively departed from them in a direction of both opposite ends are located for every unit element, respectively; a second sheet of at least one sheet formed so that a third conductor pattern is formed straddling a plurality of unit elements in a direction crossing the direction of the both opposite ends; and a plurality of resistor patterns formed for each unit element on the first and second sheets, respectively. In the laminated chip element, the first sheet and the second sheet are laminated alternately and the area of a region where the first conductor pattern and the third conductor patterns overlap differs from the area of a region where the second conductor pattern and the third conductor patterns overlap, respectively. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供其噪声消除和插入损耗等频率特性提高的层叠芯片元件。解决方案：该层压芯片元件包括连续形成的多个片材的至少一个片材的第一片材，使得沿着两个相对端的方向分别从它们分开的第一和第二导体图案位于每个单元元素; 至少一个片材的第二片材，其形成为使第三导体图案沿与两相对端的方向交叉的方向形成跨越多个单位元件; 以及分别为第一和第二片上的每个单位元件形成的多个电阻图案。在层叠芯片元件中，第一片和第二片交替层叠，并且第一导体图案和第三导体图案重叠的区域的区域与第二导体图案和第三导体图案的区域的区域不同重叠。版权所有（C）2011，JPO＆INPIT

2. 发明申请

US20070063330A1 Complex laminated chip element 审中-公开
标题翻译：复合层压芯片元件
公开(公告)号：US20070063330A1
公开(公告)日：2007-03-22
申请号：US10566810
申请日：2004-07-15
申请人： In-Kil Park , Soon-Ha Hwang , Duk-Hee Kim
发明人： In-Kil Park , Soon-Ha Hwang , Duk-Hee Kim
IPC分类号： H01L23/02
CPC分类号： H01G4/40 , H01C1/148 , H01C7/008 , H01C7/18 , H01C13/02 , H01F17/0006 , H01F27/40 , H01F2017/0026 , H01G4/232 , H01G4/35 , H03H1/02 , H03H2001/0014 , H03H2001/0085 , H03H2001/0092
摘要： The present invention relates to a laminated chip element which can be manufactured to have desired electric properties by combining various elements in accordance with the desired objectives. More particularly, the present invention relates to a laminated chip element which has superior high frequency properties and can be manufactured to control capacitance and/or inductance of the laminated chip element to a desired value. There is provided a laminated chip element, comprising at least one first sheet on which first and second conductive patterns are formed, the first and second conductive patterns being spaced apart from each other in a direction of both ends of the first sheet; and at least one second sheet on which a third conductive pattern is formed, the third conductive pattern being formed in a transverse direction of both the ends of the first sheet; wherein one ends of the first and second conductive patterns are connected to the first and second external terminals, respectively, at least one end of the third conductive pattern is connected to a third external terminal, and the first and second sheets are laminated. There is also provided a laminated chip element, comprising: at least one first sheet on which a conductive pattern is formed, the first conductive pattern consisting of first and third portions, the first and second portions being spaced apart from each other in a direction of both ends of the first sheet, the second portion connecting the first and second portions to each other to have a predetermined inductance; and at least one second sheet on which a conductive pattern is formed in a transverse direction of both the ends of the first sheet; wherein the first and second portions are connected to the first and second external terminals, respectively, at least one ends of the second conductive pattern is connected to a third external terminal, and the first and second sheets are laminated.
摘要翻译：本发明涉及层压芯片元件，其可以通过根据期望的目标组合各种元件而被制造为具有期望的电性能。更具体地说，本发明涉及一种具有优异的高频性能并且可以被制造以将层压芯片元件的电容和/或电感控制到期望值的层叠芯片元件。提供了一种层叠芯片元件，包括至少一个在其上形成有第一和第二导电图案的第一片，第一和第二导电图案在第一片的两端的方向上彼此间隔开; 以及至少一个第二片，其上形成有第三导电图案，所述第三导电图案沿所述第一片的两端的横向方向形成; 其中，所述第一和第二导电图案的一端分别连接到所述第一和第二外部端子，所述第三导电图案的至少一端连接到第三外部端子，并且所述第一和第二片材层叠。还提供了一种层叠芯片元件，包括：至少一个第一片，其上形成有导电图案，第一导电图案由第一和第三部分组成，第一和第二部分在第一和第二部分的方向上彼此间隔开所述第一片的两端，所述第二部分将所述第一部分和所述第二部分彼此连接成具有预定的电感; 以及至少一个第二片，在所述第一片的两端的横向方向上形成有导电图案; 其中所述第一和第二部分分别连接到所述第一和第二外部端子，所述第二导电图案的至少一个端部连接到第三外部端子，并且所述第一和第二片材被层叠。

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