专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07932779B2 D-class amplifier 有权
标题翻译： D级放大器
公开(公告)号：US07932779B2
公开(公告)日：2011-04-26
申请号：US12102163
申请日：2008-04-14
申请人： Toru Ido , Soichiro Ishizuka
发明人： Toru Ido , Soichiro Ishizuka
IPC分类号： H03F3/217
CPC分类号： H03F3/217
摘要： A D-class amplifier that can suppress noise generated when a D-class amplification operation is started/stopped. When a D-class amplification operation is started/stopped, the pulse widths and pulse interval of output signals Pout1, Pout2 are gradually changed, so it is possible to prevent a large variation in the signal fed as a differential signal of output signals Pout1, Pout2 to the load, and it is possible to reduce noise. That is, by gradually changing the pulse interval while keeping the pulse widths of output signals Pout1, Pout2 constant, it is possible to suppress variation in the relatively high frequency component corresponding to the component of the pulse signal. Also, by gradually changing the widths of output signals Pout1, Pout2 while keeping the pulse interval constant, it is possible to suppress variation in the relatively low frequency component corresponding to the average value of the pulse signal.
摘要翻译：可以抑制D级放大动作开始/停止时产生的噪声的D级放大器。当D级放大操作开始/停止时，输出信号Pout1，Pout2的脉冲宽度和脉冲间隔逐渐变化，因此可以防止作为输出信号Pout1的差分信号馈送的信号的大的变化， Pout2到负载，可以减少噪音。也就是说，通过在保持输出信号Pout1，Pout2的脉冲宽度保持恒定的同时逐渐改变脉冲间隔，可以抑制与脉冲信号的分量对应的相对高频分量的变化。此外，通过在保持脉冲间隔恒定的同时逐渐改变输出信号Pout1，Pout2的宽度，可以抑制与脉冲信号的平均值相对应的相对低频分量的变化。

2. 发明授权

US07623055B2 Weight level generating method and device utilizing plural weights at different time rates 有权
标题翻译：重量级产生方法和以不同时间速率利用多个权重的装置
公开(公告)号：US07623055B2
公开(公告)日：2009-11-24
申请号：US11697228
申请日：2007-04-05
申请人： Toru Ido , Soichiro Ishizuka
发明人： Toru Ido , Soichiro Ishizuka
IPC分类号： H03M1/80
CPC分类号： H03M1/0668 , H03M1/747 , H03M3/502
摘要： A weight level generator is provided. Weight level generator W has plural weight generators 5-1-5-j. At least one of said plural weight generators is used at at least two different time rates. Also, a digital-to-analog converter (DAC) using said weight generators is equipped with a digital signal source, a weight controller, and a weight generator.
摘要翻译：提供了一个重量级发生器。重量发生器W具有多个重量发生器5-1-5-j。所述多个重量发生器中的至少一个以至少两个不同的时间率使用。此外，使用所述重量发生器的数模转换器（DAC）配备有数字信号源，重量控制器和重量发生器。

3. 发明申请

US20090302942A1 D-CLASS AMPLIFIER 有权
标题翻译： D级放大器
公开(公告)号：US20090302942A1
公开(公告)日：2009-12-10
申请号：US12102163
申请日：2008-04-14
申请人： Toru Ido , Soichiro Ishizuka
发明人： Toru Ido , Soichiro Ishizuka
IPC分类号： H03F3/217
CPC分类号： H03F3/217
摘要： A D-class amplifier that can suppress noise generated when a D-class amplification operation is started/stopped. When a D-class amplification operation is started/stopped, the pulse widths and pulse interval of output signals Pout1, Pout2 are gradually changed, so it is possible to prevent a large variation in the signal fed as a differential signal of output signals Pout1, Pout2 to the load, and it is possible to reduce noise. That is, by gradually changing the pulse interval while keeping the pulse widths of output signals Pout1, Pout2 constant, it is possible to suppress variation in the relatively high frequency component corresponding to the component of the pulse signal. Also, by gradually changing the widths of output signals Pout1, Pout2 while keeping the pulse interval constant, it is possible to suppress variation in the relatively low frequency component corresponding to the average value of the pulse signal.
摘要翻译：可以抑制D级放大动作开始/停止时产生的噪声的D级放大器。当D级放大操作开始/停止时，输出信号Pout1，Pout2的脉冲宽度和脉冲间隔逐渐变化，因此可以防止作为输出信号Pout1的差分信号馈送的信号的大的变化， Pout2到负载，可以减少噪音。也就是说，通过在保持输出信号Pout1，Pout2的脉冲宽度保持恒定的同时逐渐改变脉冲间隔，可以抑制与脉冲信号的分量对应的相对高频分量的变化。此外，通过在保持脉冲间隔恒定的同时逐渐改变输出信号Pout1，Pout2的宽度，可以抑制与脉冲信号的平均值相对应的相对低频分量的变化。

4. 发明申请

US20070252743A1 DYNAMIC ELEMENT MATCHING METHOD AND DEVICE 有权
标题翻译：动态元件匹配方法和装置
公开(公告)号：US20070252743A1
公开(公告)日：2007-11-01
申请号：US11697235
申请日：2007-04-05
申请人： Toru Ido , Soichiro Ishizuka
发明人： Toru Ido , Soichiro Ishizuka
IPC分类号： H03M1/12
CPC分类号： H03M1/0668 , H03M1/747 , H03M3/502
摘要： The invention provides an improved dynamic element matching (DEM) device. The DEM device performs dynamic element matching processing at a second timing rate different from the first timing rate for the digital input. As an embodiment, the DEM device is composed of encoder 10 and feedback circuit 12. Said encoder 10 has two inputs and one output. Of the two inputs, one receives the digital input as the object for the DEM processing, and the other input receives the output of feedback circuit 12. Then, the digital output of the encoded result is generated. Said feedback circuit 12 has sampling rate converter 120 and loop filter 122 in order to perform DEM processing at a timing rate different from the timing rate for the digital input as the DEM processing object.
摘要翻译：本发明提供一种改进的动态元件匹配（DEM）装置。 DEM设备以与数字输入的第一定时速率不同的第二定时速率执行动态元素匹配处理。作为实施例，DEM设备由编码器10和反馈电路12组成。所述编码器10具有两个输入和一个输出。在两个输入中，一个接收数字输入作为DEM处理的对象，另一个输入接收反馈电路12的输出。然后，生成编码结果的数字输出。所述反馈电路12具有采样率转换器120和环路滤波器122，以便以与作为DEM处理对象的数字输入的定时速率不同的定时速率执行DEM处理。

5. 发明授权

US07557744B2 PWM driver and class D amplifier using same 有权
标题翻译： PWM驱动器和D类放大器使用相同
公开(公告)号：US07557744B2
公开(公告)日：2009-07-07
申请号：US11263453
申请日：2005-10-31
申请人： Toru Ido , Soichiro Ishizuka
发明人： Toru Ido , Soichiro Ishizuka
IPC分类号： H03M1/82
CPC分类号： H03F3/217 , H03F2200/331 , H03M3/324 , H03M3/432 , H03M3/456 , H03M3/50
摘要： The objective of the invention is to provide a class D amplifier that can reduce aliasing noise. The class D amplifier has D/A converter 10 that operates at the first sampling frequency, and PWM driver 3 that receives the output from D/A converter 10. Said PWM driver 3 operates at the second sampling frequency synchronized to the first sampling frequency. The second sampling frequency can be correlated to the delta wave frequency of the PWM driver. Also, synchronization of said first sampling frequency and said second sampling frequency can be carried out with one of said frequencies being an integer multiple of the other.
摘要翻译：本发明的目的是提供一种可以减少混叠噪声的D类放大器。 D类放大器具有以第一采样频率工作的D / A转换器10和接收D / A转换器10的输出的PWM驱动器3.所述PWM驱动器3以与第一采样频率同步的第二采样频率工作。第二采样频率可以与PWM驱动器的增量波频率相关。此外，所述第一采样频率和所述第二采样频率的同步可以执行，其中一个频率是另一个的整数倍。

6. 发明申请

US20080174362A1 VOLTAGE SUPPLY CIRCUIT AND CIRCUIT DEVICE 有权
标题翻译：电压电路和电路设备
公开(公告)号：US20080174362A1
公开(公告)日：2008-07-24
申请号：US11963089
申请日：2007-12-21
申请人： Soichiro Ishizuka , Toru Ido , Naoki Furuya , Takeshi Anzai
发明人： Soichiro Ishizuka , Toru Ido , Naoki Furuya , Takeshi Anzai
IPC分类号： G05F3/02
CPC分类号： G05F1/56
摘要： A voltage supply circuit and a circuit device can reduce the noise in the output of the circuit when the power to the circuit is turned on and off and can shorten the time required to start or stop the operation of the circuit. When the supply of power to signal processing part 10 is started or stopped, reference voltage Vref supplied to signal processing part 10 is varied continuously to reduce the high-frequency noise in the output of signal processing part 10. Also, when the setpoint value of the waveform of reference voltage Vref is generated by digital signal processing in voltage setting part 30, the desired waveform can be generated without being limited by the values of the circuit elements or the circuit configuration. The output noise of signal processing part 10 can be reduced, and the time that reference time Vref varies can be shortened.
摘要翻译：电压供应电路和电路装置可以在电路的电源接通和断开时减小电路输出的噪声，并且可以缩短启动或停止电路运行所需的时间。当向信号处理部10的供电开始或停止时，提供给信号处理部10的参考电压Vref连续变化，以降低信号处理部10的输出中的高频噪声。此外，当通过电压设定部30中的数字信号处理生成参考电压Vref的波形的设定值时，可以生成期望的波形而不受电路元件的值或电路结构的限制。可以减少信号处理部分10的输出噪声，并且缩短基准时间Vref变化的时间。

7. 发明授权

US07215271B2 Method and apparatus for forming transient response characteristics 有权
标题翻译：用于形成瞬态响应特性的方法和装置
公开(公告)号：US07215271B2
公开(公告)日：2007-05-08
申请号：US11172265
申请日：2005-06-29
申请人： Toru Ido , Soichiro Ishizuka
发明人： Toru Ido , Soichiro Ishizuka
IPC分类号： H03M1/66
CPC分类号： H03M1/0863 , H03M1/0682 , H03M1/745 , H03M1/747
摘要： Transient response generating circuit A has a first circuit 3 that generates transient response OUT1 in a first polarity direction, a second circuit 4 that generates transient response OUT2 in a second polarity direction opposite to the first polarity, and a transient response synthesizing circuit 6 that combines the transient response OUT1 in the first polarity direction and the transient response OUT2 in the second polarity direction to generate composite transient response OUTC.
摘要翻译：瞬态响应产生电路A具有在第一极性方向上产生瞬态响应OUT 1的第一电路3，产生与第一极性相反的第二极性方向的瞬态响应OUT 2的第二电路4和瞬态响应合成电路6 其将第一极性方向上的瞬态响应OUT 1和第二极性方向上的瞬态响应OUT 2组合以产生复合瞬态响应OUTC。

8. 发明授权

US07123178B2 Digital encoder and digital-to-analog converter using same 有权
标题翻译：数字编码器和使用相同的数模转换器
公开(公告)号：US07123178B2
公开(公告)日：2006-10-17
申请号：US11170908
申请日：2005-06-29
申请人： Soichiro Ishizuka , Toru Ido
发明人： Soichiro Ishizuka , Toru Ido
IPC分类号： H03M1/66
CPC分类号： H03M1/067 , H03M1/74 , H03M3/502
摘要： A digital encoder having a dynamic element matching (DEM) processor is divided into a master DEM circuit and N slave DEM circuits. The master DEM circuit encodes a multibit digital input signal (IN0) into parallel codes (C1) corresponding to the coefficient of a plurality of output nodes on the basis of a prescribed DEM algorithm. Each of the N slave DEM means (2) has 3 or more output nodes. Code (C1) from the master DEM circuit is encoded into parallel codes (C2) with the same weighting for each code and corresponding to the configuration of the 3 or more output nodes on the basis of a prescribed DEM algorithm, and the obtained parallel codes are output in parallel from 3 or more output nodes.
摘要翻译：具有动态元件匹配（DEM）处理器的数字编码器被分为主DEM电路和N个从属DEM电路。主DEM电路基于规定的DEM算法将多位数字输入信号（IN 0）编码为对应于多个输出节点的系数的并行代码（C 1）。 N从DEM装置（2）中的每一个具有3个或更多个输出节点。根据规定的DEM算法，从主DEM电路的代码（C 1）被编码成对于每个代码具有相同权重的并行代码（C 2），并对应于3个或更多个输出节点的配置，并且获得并行代码从3个以上的输出节点并行输出。

9. 发明申请

US20060007027A1 Digital encoder and digital-to-analog converter using same 有权
标题翻译：数字编码器和使用相同的数模转换器
公开(公告)号：US20060007027A1
公开(公告)日：2006-01-12
申请号：US11170908
申请日：2005-06-29
申请人： Soichiro Ishizuka , Toru Ido
发明人： Soichiro Ishizuka , Toru Ido
IPC分类号： H03M7/00
CPC分类号： H03M1/067 , H03M1/74 , H03M3/502
摘要： A digital encoder having a dynamic element matching (DEM) processor is divided into a master DEM circuit and N slave DEM circuits. The master DEM circuit encodes a multibit digital input signal (INO) into parallel codes (C1) corresponding to the coefficient of a plurality of output nodes on the basis of a prescribed DEM algorithm. Each of the N slave DEM means (2) has 3 or more output nodes. Code (C1) from the master DEM circuit is encoded into parallel codes (C2) with the same weighting for each code and corresponding to the configuration of the 3 or more output nodes on the basis of a prescribed DEM algorithm, and the obtained parallel codes are output in parallel from 3 or more output nodes.
摘要翻译：具有动态元件匹配（DEM）处理器的数字编码器被分为主DEM电路和N个从属DEM电路。主DEM电路基于规定的DEM算法将多位数字输入信号（INO）编码为对应于多个输出节点的系数的并行代码（C 1）。 N从DEM装置（2）中的每一个具有3个或更多个输出节点。根据规定的DEM算法，从主DEM电路的代码（C 1）被编码成对于每个代码具有相同权重的并行代码（C 2），并对应于3个或更多个输出节点的配置，并且获得并行代码从3个以上的输出节点并行输出。

10. 发明申请

US20070279271A1 WEIGHT LEVEL GENERATING METHOD AND DEVICE 有权
标题翻译：重量级发电方法及装置
公开(公告)号：US20070279271A1
公开(公告)日：2007-12-06
申请号：US11697228
申请日：2007-04-05
申请人： Toru Ido , Soichiro Ishizuka
发明人： Toru Ido , Soichiro Ishizuka
IPC分类号： H03M1/80
CPC分类号： H03M1/0668 , H03M1/747 , H03M3/502
摘要： A weight level generator is provided. Weight level generator W has plural weight generators 5-1-5-j. At least one of said plural weight generators is used at at least two different time rates. Also, a digital-to-analog converter (DAC) using said weight generators is equipped with a digital signal source, a weight controller, and a weight generator.
摘要翻译：提供了一个重量级发生器。重量发生器W具有多个重量发生器5-1-5-j。所述多个重量发生器中的至少一个以至少两个不同的时间速率使用。此外，使用所述重量发生器的数模转换器（DAC）配备有数字信号源，重量控制器和重量发生器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式