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1. 发明授权

US07427552B2 Method for fabricating isolation structures for flash memory semiconductor devices 有权
标题翻译：闪存半导体器件隔离结构的制造方法
公开(公告)号：US07427552B2
公开(公告)日：2008-09-23
申请号：US11556131
申请日：2006-11-02
申请人： Da Jin , Shu Shu Tang , Zuo Ya Yang
发明人： Da Jin , Shu Shu Tang , Zuo Ya Yang
IPC分类号： H01L21/76
CPC分类号： H01L27/115 , H01L27/11521
摘要： A method for fabricating integrated circuit devices, e.g., Flash memory devices, embedded Flash memory devices. The method includes providing a semiconductor substrate, e.g., silicon, silicon on insulator, epitaxial silicon. In a specific embodiment, the semiconductor substrate has a peripheral region and a cell region. The method includes forming a first dielectric layer (e.g., silicon dioxide) having a first thickness overlying a cell region and a second dielectric layer (e.g., silicon dixode) having a second thickness overlying the peripheral region. In a specific embodiment, the cell region is for Flash memory devices and/or other like structures. The method forms a pad oxide layer overlying the first dielectric layer and forms a nitride layer overlying the pad oxide layer. The method includes patterning at least the nitride layer to expose a first trench region in the peripheral region and to expose a second trench region in the cell region, while a portion of the first dielectric layer having the first thickness in the cell region is maintained. The method includes forming a first trench structure having a first depth in the first trench region, while the portion of the first dielectric layer having the first thickness in the cell region protects the second trench region. The method includes removing the portion of the first dielectric layer to expose the second trench region. In a specific embodiment, the method includes subjecting the first trench region, including the first trench structure, and the second trench region with an etching process to continue to form the first trench structure from the first depth to a second depth and to form a second trench structure having a third depth within the second trench region. In the third depth is less than the second depth.
摘要翻译：集成电路器件的制造方法，例如闪存器件，嵌入式闪存器件。该方法包括提供半导体衬底，例如硅，绝缘体上的硅，外延硅。在具体实施例中，半导体衬底具有周边区域和单元区域。该方法包括形成具有覆盖在单元区域上的第一厚度的第一介电层（例如二氧化硅）和覆盖周边区域的第二厚度的第二介电层（例如硅二极管）。在特定实施例中，单元区域用于闪速存储器件和/或其它类似结构。该方法形成覆盖在第一介电层上的衬垫氧化层，并形成覆盖衬垫氧化物层的氮化物层。该方法包括图案化至少该氮化物层以露出外围区域中的第一沟槽区域并露出该单元区域中的第二沟槽区域，同时保持该单元区域中具有第一厚度的第一介电层的一部分。该方法包括在第一沟槽区域中形成具有第一深度的第一沟槽结构，而在单元区域中具有第一厚度的第一介电层的部分保护第二沟槽区。该方法包括移除第一电介质层的部分以暴露第二沟槽区域。在一个具体实施例中，该方法包括用蚀刻工艺对包括第一沟槽结构的第一沟槽区域和第二沟槽区域进行处理，以继续从第一深度到第二深度形成第一沟槽结构，并形成第二沟槽区域沟槽结构在第二沟槽区域内具有第三深度。在第三深度小于第二深度。

2. 发明申请

US20070128804A1 Method for Fabricating Isolation Structures for Flash Memory Semiconductor Devices 有权
标题翻译：闪存半导体器件隔离结构的制作方法
公开(公告)号：US20070128804A1
公开(公告)日：2007-06-07
申请号：US11556131
申请日：2006-11-02
申请人： Da Jin , Shu Shu Tang , Zuo Yang
发明人： Da Jin , Shu Shu Tang , Zuo Yang
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L27/115 , H01L27/11521
摘要： A method for fabricating integrated circuit devices, e.g., Flash memory devices, embedded Flash memory devices. The method includes providing a semiconductor substrate, e.g., silicon, silicon on insulator, epitaxial silicon. In a specific embodiment, the semiconductor substrate has a peripheral region and a cell region. The method includes forming a first dielectric layer (e.g., silicon dioxide) having a first thickness overlying a cell region and a second dielectric layer (e.g., silicon dixode) having a second thickness overlying the peripheral region. In a specific embodiment, the cell region is for Flash memory devices and/or other like structures. The method forms a pad oxide layer overlying the first dielectric layer and forms a nitride layer overlying the pad oxide layer. The method includes patterning at least the nitride layer to expose a first trench region in the peripheral region and to expose a second trench region in the cell region, while a portion of the first dielectric layer having the first thickness in the cell region is maintained. The method includes forming a first trench structure having a first depth in the first trench region, while the portion of the first dielectric layer having the first thickness in the cell region protects the second trench region. The method includes removing the portion of the first dielectric layer to expose the second trench region. In a specific embodiment, the method includes subjecting the first trench region, including the first trench structure, and the second trench region with an etching process to continue to form the first trench structure from the first depth to a second depth and to form a second trench structure having a third depth within the second trench region. In the third depth is less than the second depth.
摘要翻译：集成电路器件的制造方法，例如闪存器件，嵌入式闪存器件。该方法包括提供半导体衬底，例如硅，绝缘体上的硅，外延硅。在具体实施例中，半导体衬底具有周边区域和单元区域。该方法包括形成具有覆盖在单元区域上的第一厚度的第一介电层（例如二氧化硅）和覆盖周边区域的第二厚度的第二介电层（例如硅二极管）。在特定实施例中，单元区域用于闪速存储器件和/或其它类似结构。该方法形成覆盖在第一介电层上的衬垫氧化层，并形成覆盖衬垫氧化物层的氮化物层。该方法包括图案化至少该氮化物层以露出外围区域中的第一沟槽区域并露出该单元区域中的第二沟槽区域，同时保持该单元区域中具有第一厚度的第一介电层的一部分。该方法包括在第一沟槽区域中形成具有第一深度的第一沟槽结构，而在单元区域中具有第一厚度的第一介电层的部分保护第二沟槽区。该方法包括移除第一电介质层的部分以暴露第二沟槽区域。在一个具体实施例中，该方法包括用蚀刻工艺对包括第一沟槽结构的第一沟槽区域和第二沟槽区域进行处理，以继续从第一深度到第二深度形成第一沟槽结构，并形成第二沟槽区域沟槽结构在第二沟槽区域内具有第三深度。在第三深度小于第二深度。

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