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1. 发明授权

US5798544A Semiconductor memory device having trench isolation regions and bit lines formed thereover 失效
标题翻译：具有形成在其上的沟槽隔离区域和位线的半导体存储器件
公开(公告)号：US5798544A
公开(公告)日：1998-08-25
申请号：US242345
申请日：1994-05-13
申请人： Shuichi Ohya , Masato Sakao , Yoshihiro Takaishi , Kiyonori Kajiyana , Takeshi Akimoto , Shizuo Oguro , Seiichi Shishiguchi
发明人： Shuichi Ohya , Masato Sakao , Yoshihiro Takaishi , Kiyonori Kajiyana , Takeshi Akimoto , Shizuo Oguro , Seiichi Shishiguchi
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108 , H01L29/76
CPC分类号： H01L27/10823 , H01L27/10808
摘要： Disclosed herein is a semiconductor memory device including a plurality of memory cells each includes an active region which is defined in a column direction by a pair of trench isolation regions formed in a semiconductor substrate and in a row direction by an isolation gate conductor lines formed on a first gate insulating film covering the substrate, a source and a drain region selectively formed in the active region to define a channel region of a cell transistor, a second gate insulating film formed on the channel region, a word line formed on the second gate insulating film, a first insulating film covering the active region and the word line, a bit line formed on the first insulating film to overlap with the isolation gate conductor, a bit line connection conductor formed in the first insulating film to connect the drain region to the bit line with being in contact with the sidewall surface of the bit line, a second insulating film covering the bit line and the first insulating film, and a storage capacitor having a capacitor electrode connected to the source region through a contact hole provided in the first and second insulating film.
摘要翻译：这里公开了一种半导体存储器件，其包括多个存储单元，每个存储单元包括有源区，该有源区通过在半导体衬底中形成的一对沟槽隔离区而在列方向上限定，并且在行方向上由隔离栅导体线形成覆盖基板的第一栅极绝缘膜，选择性地形成在有源区中的源极和漏极区域，以限定单元晶体管的沟道区，形成在沟道区上的第二栅极绝缘膜，形成在第二栅极上的字线绝缘膜，覆盖有源区和字线的第一绝缘膜，形成在第一绝缘膜上以与隔离栅导体重叠的位线;形成在第一绝缘膜中的位线连接导体，以将漏区连接到位线与位线的侧壁表面接触，覆盖位线的第二绝缘膜和第一绝缘f 以及具有通过设置在第一和第二绝缘膜中的接触孔连接到源极区的电容器电极的存储电容器。

2. 发明授权

US5443661A SOI (silicon on insulator) substrate with enhanced gettering effects 失效
标题翻译： SOI（绝缘体上硅）衬底具有增强的吸杂效应
公开(公告)号：US5443661A
公开(公告)日：1995-08-22
申请号：US280994
申请日：1994-07-27
申请人： Shizuo Oguro , Tatsuya Suzuki
发明人： Shizuo Oguro , Tatsuya Suzuki
IPC分类号： H01L21/02 , H01L21/322 , H01L21/76 , H01L27/12 , H01L21/20
CPC分类号： H01L21/3226 , Y10S148/012
摘要： A silicon-on-insulator (SOI) substrate is arranged such that a polycrystalline silicon film which functions as a gettering site for heavy metals is provided on a first single crystal silicon substrate, a silicon oxide island film is partially provided in a polycrystalline silicon film, and a second single crystal silicon substrate is provided on an entire upper surface of the polycrystalline silicon film. An element isolation trench extends from an upper surface of the second single crystal silicon substrate to an upper surface of the first single crystal silicon substrate, and a silicon oxide film is buried in the element isolation trench. The SOI substrate thus constituted has a high gettering effect for heavy metals.
摘要翻译：绝缘体上硅（SOI）衬底被布置成使得在第一单晶硅衬底上提供用作重金属的吸杂位点的多晶硅膜，部分地将氧化硅岛膜设置在多晶硅膜中并且在多晶硅膜的整个上表面上设置第二单晶硅基板。元件隔离沟槽从第二单晶硅衬底的上表面延伸到第一单晶硅衬底的上表面，并且氧化硅膜被掩埋在元件隔离沟槽中。由此构成的SOI衬底对重金属具有高吸气效果。

3. 发明授权

US5714415A Method of forming thin semiconductor film 失效
标题翻译：薄半导体膜的形成方法
公开(公告)号：US5714415A
公开(公告)日：1998-02-03
申请号：US592991
申请日：1996-01-29
申请人： Shizuo Oguro
发明人： Shizuo Oguro
IPC分类号： H01L21/225 , H01L21/20 , H01L21/205
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/02587 , H01L21/0262 , H01L21/02664
摘要： A method of forming a thin semiconductor film including an impurity for obtaining a conductivity includes the step of depositing a thin amorphous silicon film by chemical vapor deposition using silane as a deposition source gas at a deposition rate of at least 3 nm/minute while introducing the impurity, and the step of crystallizing the deposited thin amorphous silicon film by annealing.
摘要翻译：形成包含用于获得导电性的杂质的薄的半导体膜的方法包括通过化学气相沉积法以至少3nm /分钟的沉积速率使用硅烷作为沉积源气体沉积薄的非晶硅膜的步骤，同时引入杂质，以及通过退火使沉积的薄的非晶硅膜结晶的步骤。

4. 发明授权

US5371039A Method for fabricating capacitor having polycrystalline silicon film 失效
标题翻译：制造具有多晶硅膜的电容器的方法
公开(公告)号：US5371039A
公开(公告)日：1994-12-06
申请号：US19359
申请日：1993-02-18
申请人： Shizuo Oguro
发明人： Shizuo Oguro
IPC分类号： H01L21/02 , H01L21/20 , H01L21/205 , H01L21/223
CPC分类号： H01L28/60 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/0262 , H01L21/02667
摘要： A method of fabricating a semiconductor device, in particular of forming a polysilicon film on a step portion of an insulation film made by a trench or a contact hole is disclosed which includes the steps of depositing an amorphous silicon film on the step portion while doping impurities into the amorphous silicon film and carrying out heat treatment to convert the amorphous silicon film into a polycrystalline silicon film, thereby the polysilicon film on a step portion being formed.
摘要翻译：公开了一种制造半导体器件的方法，特别是在由沟槽或接触孔制成的绝缘膜的台阶上形成多晶硅膜，其包括以下步骤：在台阶部分上沉积非晶硅膜，同时掺杂杂质进入非晶硅膜并进行热处理以将非晶硅膜转化为多晶硅膜，从而形成台阶部分上的多晶硅膜。

5. 发明授权

US5464795A Method of forming polycrystalline silicon thin films for semiconductor devices 失效
标题翻译：形成半导体器件多晶硅薄膜的方法
公开(公告)号：US5464795A
公开(公告)日：1995-11-07
申请号：US203559
申请日：1994-03-01
申请人： Shizuo Oguro
发明人： Shizuo Oguro
IPC分类号： H01L21/20 , H01L21/205
CPC分类号： H01L21/02381 , H01L21/02488 , H01L21/02494 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/02587 , H01L21/0262
摘要： A semiconductor thin film is formed by depositing an amorphous silicon thin film and heat-treating the deposited amorphous silicon thin film. The amorphous silicon thin film is formed by a chemical vapor deposition (CVD) process while a dopant impurity is introduced, the film being not thicker than 50 nanometers. In the reaction gases used, the ratio (D/S) between the numbers S and D of atoms of silicon and dopant impurity in reaction gases is as large as 0.05.about.0.2. The polycrystalline silicon thin film thus formed is with reduced electrical resistivities.
摘要翻译：通过沉积非晶硅薄膜并对沉积的非晶硅薄膜进行热处理来形成半导体薄膜。通过化学气相沉积（CVD）工艺形成非晶硅薄膜，同时引入掺杂杂质，该膜不超过50纳米。在所使用的反应气体中，反应气体中硅原子和掺杂剂杂质数S和D之间的比（D / S）大至0.05差异0.2。这样形成的多晶硅薄膜具有降低的电阻率。

6. 发明授权

US5242855A Method of fabricating a polycrystalline silicon film having a reduced resistivity 失效
标题翻译：制造电阻率降低的多晶硅膜的方法
公开(公告)号：US5242855A
公开(公告)日：1993-09-07
申请号：US953137
申请日：1992-09-29
申请人： Shizuo Oguro
发明人： Shizuo Oguro
IPC分类号： H01L21/20 , H01L21/321
CPC分类号： H01L21/321
摘要： Disclosed is a method of forming a polycrystalline silicon film on a silicon oxide film in which the polycrystalline silicon film includes crystal grains having a large size, typically 4 micrometers, thereby permitting the resistivity of the polycrystalline silicon film to effectively be reduced. An amorphous silicon film is deposited on the silicon oxide film by using a chemical vapor deposition in which the flow rate of impurity gas remains at zero during an initial deposition, after which the flow rate is gradually increased from zero to a predetermined value during a final deposition. Thus, the amorphous silicon film comprises double layers, or an impurity unmixed region abutting the silicon oxide film and an impurity mixed region. After that, by a heat treatment, the amorphous silicon film is crystallized to form a polycrystalline silicon film. Concurrently, the impurity diffusion is accomplished.
摘要翻译：公开了一种在氧化硅膜上形成多晶硅膜的方法，其中多晶硅膜包括通常为4微米的大尺寸的晶粒，从而有效地降低了多晶硅膜的电阻率。通过使用在初始沉积期间杂质气体的流量保持为零的化学气相沉积，在氧化硅膜上沉积非晶硅膜，之后在最终沉积期间流速从零逐渐增加到预定值沉积因此，非晶硅膜包括双层或邻接氧化硅膜的杂质非混合区域和杂质混合区域。之后，通过热处理，使非晶硅膜结晶化，形成多晶硅膜。同时，完成杂质扩散。

7. 发明授权

US6074478A Method of facet free selective silicon epitaxy 失效
标题翻译：无面选择性硅外延的方法
公开(公告)号：US6074478A
公开(公告)日：2000-06-13
申请号：US6880
申请日：1998-01-14
申请人： Shizuo Oguro
发明人： Shizuo Oguro
IPC分类号： H01L21/205 , C30B25/02 , C30B29/06 , C30B23/02
CPC分类号： C30B29/06 , C30B25/02
摘要： A flat selective silicon epitaxial thin film in which facet formation and loading effect are suppressed is grown by using a conventional LPCVD system which does not require an ultrahigh vacuum environment. Raw material gases for film formation and atomic hydrogen formed in an atomic hydrogen formation chamber 2 installed separately from a reaction chamber is introduced into the reaction chamber, at a growth temperature in the range of 750-900.degree. C. and under a reaction chamber pressure in the range of 1-30 Torr.
摘要翻译：通过使用不需要超高真空环境的常规LPCVD系统来生长其中抑制小平面形成和负载效应的扁平选择性硅外延薄膜。在与反应室分开设置的原子氢形成室2中形成的用于成膜的原料气体和原子氢气在750-900℃的生长温度和反应室压力下被引入反应室在1-30乇的范围内。

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