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1. 发明授权

US06426660B1 Duty-cycle correction circuit 有权
标题翻译：占空比校正电路
公开(公告)号：US06426660B1
公开(公告)日：2002-07-30
申请号：US09943665
申请日：2001-08-30
申请人： Shiu C. Ho , David W. Blum
发明人： Shiu C. Ho , David W. Blum
IPC分类号： H03K3017
CPC分类号： H03K5/1565 , H03K5/00006
摘要： A duty-cycle correction circuit corrects a clock with arbitrary duty-cycle to a 50% duty-cycle clock, with its original frequency. The device acts to translate a non-50% duty-cycle clock to an accurate 50% duty-cycle clock by utilizing a divide-by-2 frequency divider and a multiply-by-2 clock doubler to achieve conversion. The duty-cycle correction circuit increases the translation back to its original frequency while using an analog negative feedback to maintain an accurate 50% duty cycle.
摘要翻译：占空比校正电路以任意占空比校正具有原始频率的50％占空比时钟的时钟。该器件通过利用2分频分频器和2乘法倍频器实现转换，将非50％占空比时钟转换为精确的50％占空比时钟。占空比校正电路在使用模拟负反馈保持精确的50％占空比时，将平移增加到原始频率。

2. 发明授权

US06956417B2 Leakage compensation circuit 失效
标题翻译：漏电补偿电路
公开(公告)号：US06956417B2
公开(公告)日：2005-10-18
申请号：US10707123
申请日：2003-11-21
申请人： Kerry Bernstein , Anthony R. Bonaccio , John A. Fifield , Allen P. Haar , Shiu C. Ho , Terence B. Hook , Michael A. Soma , Stephen D. Wyatt
发明人： Kerry Bernstein , Anthony R. Bonaccio , John A. Fifield , Allen P. Haar , Shiu C. Ho , Terence B. Hook , Michael A. Soma , Stephen D. Wyatt
IPC分类号： H03L7/06 , H03L7/089 , H03L7/093
CPC分类号： H03L7/093 , H03L7/0891
摘要： A circuit, including: a capacitor coupled between a first circuit node and a second circuit node and that leaks a leakage current from the first circuit node to the second circuit node; and a compensation circuit adapted to supply a compensatory current to compensate for the leakage current to the first circuit node.
摘要翻译：一种电路，包括：电容器，耦合在第一电路节点和第二电路节点之间，并且泄漏电流从第一电路节点泄漏到第二电路节点; 以及补偿电路，其适于提供补偿电流以补偿到第一电路节点的漏电流。

3. 发明授权

US06946887B2 Phase frequency detector with programmable minimum pulse width 失效
标题翻译：具有可编程最小脉冲宽度的相位频率检测器
公开(公告)号：US06946887B2
公开(公告)日：2005-09-20
申请号：US10707178
申请日：2003-11-25
申请人： Shiu C. Ho
发明人： Shiu C. Ho
IPC分类号： H03L7/089 , H03L7/06
CPC分类号： H03L7/0891
摘要： A structure and associated method for reducing a static phase error in a phase-locked loop circuit. The phase-locked loop circuit comprises a voltage controlled oscillator and a phase frequency detector. The voltage controlled oscillator is adapted to provide a first clock signal comprising a first frequency. The phase frequency detector is adapted to compare the first clock signal comprising the first frequency to a reference clock signal comprising a reference frequency. The phase frequency detector comprises a programmable circuit adapted to vary a minimum pulse width of an increment pulse and a minimum pulse width of a decrement pulse. The programmable circuit is further adapted to reduce a static phase error of the phase locked-loop circuit.
摘要翻译：一种降低锁相环电路静态相位误差的结构和相关方法。锁相环电路包括压控振荡器和相位频率检测器。压控振荡器适于提供包括第一频率的第一时钟信号。相位频率检测器适于将包括第一频率的第一时钟信号与包括参考频率的参考时钟信号进行比较。相位频率检测器包括可编程电路，其适于改变增量脉冲的最小脉冲宽度和递减脉冲的最小脉冲宽度。可编程电路还适于减小锁相环电路的静态相位误差。

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