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1. 发明授权

US08243564B2 Misjudgment correction circuit and optical disk drive 失效
标题翻译：误判修正电路和光盘驱动器
公开(公告)号：US08243564B2
公开(公告)日：2012-08-14
申请号：US12385381
申请日：2009-04-07
申请人： Shinya Nouchi , Kimimasa Senba , Kenichi Ishida
发明人： Shinya Nouchi , Kimimasa Senba , Kenichi Ishida
IPC分类号： G11B7/00
CPC分类号： G11B7/0053
摘要： Disclosed herein is a misjudgment correction circuit, including, an edge detection section configured to detect, in a binarized full addition signal obtained by adding first and second signals of the same or opposite polarity, edges at which the logic value of the binarized signal changes, a push-pull signal acquisition section configured to acquire a binarized push-pull signal obtained by subtracting the second signal from the first signal, a majority decision calculation section configured to acquire, in chronologic order, a plurality of logic values of the push-pull signal between the two adjacent edges so as to determine, by a majority decision, the more numerous of the two logic values, and a wave correction section configured to correct the push-pull signal between the edges to the more numerous logic value determined by the majority decision calculation section.
摘要翻译：这里公开了一种错误校正电路，包括：边缘检测部分，被配置为在通过将相关或相反极性的第一和第二信号相加或者相反的二极化信号的逻辑值改变的边缘进行二值化的全相加信号中检测，推挽信号获取部，被配置为获取通过从第一信号中减去第二信号而获得的二值化推挽信号;多数决定计算部，被配置为按时间顺序获取推挽的多个逻辑值在两个相邻边缘之间的信号，以便通过多数决定来确定两个逻辑值中的更多个，以及被配置为将边缘之间的推挽信号校正到由多个逻辑值确定的更多的逻辑值的波形校正部分多数决策计算部分。

2. 发明申请

US20090279396A1 Misjudgment correction circuit and optical disk drive 失效
标题翻译：误判修正电路和光盘驱动器
公开(公告)号：US20090279396A1
公开(公告)日：2009-11-12
申请号：US12385381
申请日：2009-04-07
申请人： Shinya Nouchi , Kimimasa Senba , Kenichi Ishida
发明人： Shinya Nouchi , Kimimasa Senba , Kenichi Ishida
IPC分类号： G11B7/00
CPC分类号： G11B7/0053
摘要： Disclosed herein is a misjudgment correction circuit, including, an edge detection section configured to detect, in a binarized full addition signal obtained by adding first and second signals of the same or opposite polarity, edges at which the logic value of the binarized signal changes, a push-pull signal acquisition section configured to acquire a binarized push-pull signal obtained by subtracting the second signal from the first signal, a majority decision calculation section configured to acquire, in chronologic order, a plurality of logic values of the push-pull signal between the two adjacent edges so as to determine, by a majority decision, the more numerous of the two logic values, and a wave correction section configured to correct the push-pull signal between the edges to the more numerous logic value determined by the majority decision calculation section.
摘要翻译：这里公开了一种错误校正电路，包括：边缘检测部分，被配置为在通过将相关或相反极性的第一和第二信号相加或者相反的二极化信号的逻辑值改变的边缘进行二值化的全相加信号中检测，推挽信号获取部，被配置为获取通过从第一信号中减去第二信号而获得的二值化推挽信号;多数决定计算部，被配置为按时间顺序获取推挽的多个逻辑值在两个相邻边缘之间的信号，以便通过多数决定来确定两个逻辑值中的更多个，以及被配置为将边缘之间的推挽信号校正到由多个逻辑值确定的更多的逻辑值的波形校正部分多数决策计算部分。

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