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1. 发明申请

US20070035998A1 Nonvolatile memory apparatus 审中-公开
标题翻译：非易失存储器
公开(公告)号：US20070035998A1
公开(公告)日：2007-02-15
申请号：US11581690
申请日：2006-10-17
申请人： Takayuki Tamura , Yoshinori Takase , Shinichi Shuto , Yasuhiro Nakamura , Chiaki Kumahara
发明人： Takayuki Tamura , Yoshinori Takase , Shinichi Shuto , Yasuhiro Nakamura , Chiaki Kumahara
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/06 , G11C2211/5641
摘要： Disclosed is a nonvolatile memory apparatus in which a nonvolatile memory and a controller are mounted and which realizes improved performance of read/write speeds and improved resistance to a retention error. A nonvolatile memory can store information of two bits or more, and can perform a first reading operation of outputting information read from a nonvolatile memory cell as 1-bit information and a second reading operation of outputting the read information as 2-bit information. A controller performs the first reading operation to read first information from the nonvolatile memory and performs the second reading operation to read second information. The reading speed of the first reading operation is faster than that of the second reading operation. In writing to a first area to be read, by using either a voltage in the upper-limit threshold voltage distribution or a voltage in the lower-limit threshold voltage distribution as a threshold voltage, resistance to a retention error of the first information is improved.
摘要翻译：公开了一种非易失性存储装置，其中安装了非易失性存储器和控制器，并且实现了读/写速度的改进的性能和改进的保持误差的抵抗力。非易失性存储器可以存储两位以上的信息，并且可以执行将从非易失性存储单元读取的信息作为1位信息输出的第一读取操作和作为2位信息输出读取信息的第二读取操作。控制器执行第一读取操作以从非易失性存储器读取第一信息，并执行第二读取操作以读取第二信息。第一读取操作的读取速度比第二读取操作的读取速度更快。在写入要读取的第一区域中，通过使用上限阈值电压分布中的电压或下限阈值电压分布中的电压作为阈值电压，改善对第一信息的保留误差的抵抗力。

2. 发明授权

US07269748B2 System for preventing errors upon ejection of a memory card from a slot 有权
标题翻译：用于在从存储卡弹出存储卡时防止错误的系统
公开(公告)号：US07269748B2
公开(公告)日：2007-09-11
申请号：US10712996
申请日：2003-11-17
申请人： Shinichi Shuto , Takayuki Tamura , Chiaki Kumahara
发明人： Shinichi Shuto , Takayuki Tamura , Chiaki Kumahara
IPC分类号： G06F1/00 , G06F13/00 , H05K7/10
CPC分类号： G06F1/305
摘要： Disclosed herewith is a semiconductor processing system such as a card type electronic device, which can easily cope with an error caused by power shutoff that occurs when the card is ejected. The semiconductor processing system is provided with an interface control circuit and a processing circuit and receives operation power from an external device such as a card slot when it is inserted therein. According to a first aspect of the present invention for coping with an error caused by power shutoff that occurs when the card is ejected, the interface control circuit, when the card is ejected from the card slot, detects a potential change to occur at a first external terminal to be disconnected from a predetermined terminal of the card slot before the power supply from the card slot is shut off, then instructs the processing circuit that is active to perform an ending processing. The semiconductor processing system can end the processing by itself before the power supply stops completely.
摘要翻译：这里公开了一种诸如卡型电子设备的半导体处理系统，其可以容易地处理当卡被弹出时发生的由电源关闭引起的错误。半导体处理系统设置有接口控制电路和处理电路，并且当插入其中时从诸如卡槽的外部设备接收操作电力。根据本发明的第一方面，为了应对当卡被弹出时发生的由电源关闭引起的错误，当卡从卡插槽中弹出时，接口控制电路检测到第一次发生的潜在变化在从卡槽供电之前将外部终端从卡槽的预定终端断开，然后指示有效的处理电路执行结束处理。在电源完全停止之前，半导体处理系统可以自己结束处理。

3. 发明申请

US20120221773A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120221773A1
公开(公告)日：2012-08-30
申请号：US13404883
申请日：2012-02-24
申请人： Shinichi SHUTO , Takayuki Tamura , Noriyuki Kotani , Hiroyasu Tominaga
发明人： Shinichi SHUTO , Takayuki Tamura , Noriyuki Kotani , Hiroyasu Tominaga
IPC分类号： G06F12/00
CPC分类号： G06F11/1068 , G11C16/3431
摘要： The disclosed invention provides a technique for efficiently avoiding read disturbance. A nonvolatile semiconductor memory device includes a nonvolatile memory unit and a controller that can control refresh processing for rewriting data in a block of blocks assumed to be erasable units in the nonvolatile memory unit into anther block different from the block. The controller sets up a first area and a second area different from the first area in the nonvolatile memory unit and, each time a refresh trigger occurs, executes refresh processing for the first area and the second area, such that a refresh frequency of data in the first area will become higher than a refresh frequency of data in the second area. Thereby, it is possible to efficiently avoid read disturbance when read access is repeated.
摘要翻译：所公开的发明提供了一种有效避免读取干扰的技术。非易失性半导体存储器件包括非易失性存储器单元和控制器，其可以控制刷新处理，以将在非易失性存储器单元中被假定为可擦除单元的块中的数据重写为与该块不同的另一块。所述控制器设置与所述非易失性存储器单元中的所述第一区域不同的第一区域和第二区域，并且每次刷新触发发生时，对所述第一区域和所述第二区域执行刷新处理，第一区域将变得高于第二区域中的数据刷新频率。因此，当重复读取访问时，可以有效地避免读取干扰。

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