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    • 7. 发明授权
    • Method of and apparatus for interfacing buses operating at different speeds
    • 用于以不同速度操作的总线的接口的方法和装置
    • US07334073B2
    • 2008-02-19
    • US11142463
    • 2005-06-02
    • Sang-ik ChoiShin-wook KangHyang-suk Park
    • Sang-ik ChoiShin-wook KangHyang-suk Park
    • G06F13/36
    • G06F13/405Y02D10/14Y02D10/151
    • The present invention relates to a bridge for interfacing buses within an embedded system. There is provided a method of interfacing a first bus and a second bus operating at different speeds, the method includes counting a match value assigned to a predetermined peripheral device among peripheral devices connected to the second bus for each cycle of a clock signal received from the first bus, and keeping a read state or a write state for the predetermined peripheral device by continuously outputting a read signal or a write signal for the predetermined peripheral device to the second bus, during the counting of the match value. According to the present invention, it is not necessary to operate depending on a peripheral device operating at the lowest speed among peripheral devices, and not necessary to add wrappers to the peripheral devices, by employing the AHB-to-ISA bridge variably adjusting the output times of output signals to an ISA bus.
    • 本发明涉及一种用于在嵌入式系统内接口总线的桥接器。 提供了一种接口第一总线和以不同速度工作的第二总线的方法,该方法包括对从第二总线连接到第二总线的外围设备分配给与从第二总线接收的时钟信号的每个周期相匹配的匹配值进行计数 并且在匹配值的计数期间,通过连续地向第二总线输出用于预定的外围设备的读取信号或写入信号,为预定的外围设备保持读取状态或写入状态。 根据本发明,不需要根据外围设备中以最低速度操作的外围设备进行操作,并且不需要通过使用可变地调整输出的AHB-ISA桥接器向外围设备添加封装 输出信号到ISA总线的次数。
    • 8. 发明申请
    • Memory control apparatus and method for scheduling commands
    • 用于调度命令的存储器控​​制装置和方法
    • US20050289319A1
    • 2005-12-29
    • US11088793
    • 2005-03-25
    • Shin-wook Kang
    • Shin-wook Kang
    • G06F12/02G06F12/00G06F13/16G06F13/18
    • G06F13/1631
    • Provided are a memory control apparatus and method for controlling an order of processing memory access commands from a plurality of master devices when the master devices access a memory to improve a processing speed. The memory controller includes a command queue receiving memory access commands from at least one master device and storing the memory access commands; a determination unit analyzing addresses of a memory, which will be accessed by the received commands, to control an order of processing the stored commands; and a command interpreter interpreting a command output under the control of the determination unit to output an address related signal. Accordingly, a command processing speed is remarkably improved without increasing a system size.
    • 提供一种用于当主设备访问存储器以提高处理速度时从多个主设备控制处理存储器访问命令的顺序的存储器控​​制设备和方法。 存储器控制器包括从至少一个主设备接收存储器访问命令并存储存储器访问命令的命令队列; 确定单元,分析将由所接收的命令访问的存储器的地址,以控制处理存储的命令的顺序; 以及命令解释器,其在所述确定单元的控制下解释命令输出,以输出地址相关信号。 因此,在不增加系统尺寸的情况下,命令处理速度显着提高。