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1. 发明授权

US06677199B1 Structure for preventing salicide bridging and method thereof 有权
公开(公告)号：US06677199B1
公开(公告)日：2004-01-13
申请号：US10186619
申请日：2002-07-02
申请人： Tsai-Fu Chang , Shih Lin Chu , Ching Pen Yeh
发明人： Tsai-Fu Chang , Shih Lin Chu , Ching Pen Yeh
IPC分类号： H01L21336
CPC分类号： H01L27/10885 , H01L27/1052 , H01L27/10891 , H01L27/10894 , H01L27/11531 , H01L29/665 , Y10S438/926
摘要： A semiconductor device having a memory array that includes a plurality of substantially parallel word lines, a plurality of substantially parallel bit lines, wherein each of the plurality of the word lines is substantially perpendicular to each of the plurality of the bit lines, a first dummy word line disposed at a periphery of the memory array, wherein the first dummy word line is substantially parallel to the plurality of word lines and overlaps at least two non-adjacent bit lines.

2. 发明授权

US06797534B1 Method of integrating the fabrication process for integrated circuits and MEM devices 有权
标题翻译：集成电路和MEM器件制造工艺的集成方法
公开(公告)号：US06797534B1
公开(公告)日：2004-09-28
申请号：US10418121
申请日：2003-04-18
申请人： Shuo-Lin Tu , Lu-Shan Chiang , Shih-Lin Chu
发明人： Shuo-Lin Tu , Lu-Shan Chiang , Shih-Lin Chu
IPC分类号： H01L2100
CPC分类号： B81C1/00246 , B81C2203/0735
摘要： A method of forming a MEM device with an integrated circuit that includes providing a semiconductor substrate including a first region and a second region, forming an integrated circuit device on the first region, forming a first insulating layer on the semiconductor substrate, etching the first insulating layer to form a first dielectric layer on the first region and a second dielectric layer on the second region spaced apart from the first dielectric layer, forming a second insulating layer over the semiconductor substrate, the first dielectric layer and the second dielectric layer, etching the second insulating layer to expose the first dielectric layer, forming a third insulating layer over the semiconductor substrate, the second insulatng layer and the first dielectric layer, etching the third insulating layer to form a plurality of vias, and forming a metal layer over the semiconductor substrate to fill the vias.
摘要翻译：一种用集成电路形成MEM器件的方法，该集成电路包括提供包括第一区域和第二区域的半导体衬底，在第一区域上形成集成电路器件，在半导体衬底上形成第一绝缘层，蚀刻第一绝缘层层，以在第一区域上形成第一电介质层，并且在第二区域上与第一介电层隔开的第二电介质层，在半导体衬底，第一介电层和第二电介质层上形成第二绝缘层，蚀刻第二绝缘层以暴露第一介电层，在半导体衬底上形成第三绝缘层，第二绝缘层和第一介电层，蚀刻第三绝缘层以形成多个通孔，并在半导体上形成金属层底物填充通孔。

3. 发明授权

US06723649B2 Method of fabricating a semiconductor memory device 有权
标题翻译：制造半导体存储器件的方法
公开(公告)号：US06723649B2
公开(公告)日：2004-04-20
申请号：US10157819
申请日：2002-05-31
申请人： Tsai-Fu Chang , Shih-Lin Chu , Ching-Pen Yeh
发明人： Tsai-Fu Chang , Shih-Lin Chu , Ching-Pen Yeh
IPC分类号： H01L21302
CPC分类号： H01L27/11253 , H01L21/26586 , H01L27/112
摘要： A method of fabricating a semiconductor memory device, particularly a mask ROM. A sacrificial oxide layer is formed on a silicon substrate and then a photoresist layer is formed on the sacrificial oxide layer. The photoresist layer is patterned to form a plurality of openings where bit lines are to extend respectively. Taking the patterned photoresist layer as a mask, arsenic ions are implanted into the silicon substrate through the openings and then boron ions are implanted into the silicon substrate through the openings. The implantation depth of boron ions are deeper than arsenic ions. The photoresist layer and the sacrificial oxide layer are removed after implantation. A gate oxide and a field oxide are grown simultaneously on the non-implanted and the implanted regions of the semiconductor layers respectively and a gate conductive layer is deposited on the silicon substrate.
摘要翻译：一种制造半导体存储器件，特别是掩膜ROM的方法。在硅衬底上形成牺牲氧化物层，然后在牺牲氧化物层上形成光致抗蚀剂层。图案化光致抗蚀剂层以形成多个开口，其中位线将分别延伸。将图案化的光致抗蚀剂层作为掩模，通过开口将砷离子注入到硅衬底中，然后通过开口将硼离子注入到硅衬底中。硼离子的注入深度比砷离子深。植入后去除光致抗蚀剂层和牺牲氧化物层。在半导体层的非注入区域和注入区域上同时生长栅极氧化物和场氧化物，并且在硅衬底上沉积栅极导电层。

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