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1. 发明授权

US08610456B2 Load detecting impedance matching buffer 有权
标题翻译：负载检测阻抗匹配缓冲器
公开(公告)号：US08610456B2
公开(公告)日：2013-12-17
申请号：US13241516
申请日：2011-09-23
申请人： Liviu Chiaburu , Shahin Mehdizad Taleie , Dongwon Seo , Roy B. Silverstein
发明人： Liviu Chiaburu , Shahin Mehdizad Taleie , Dongwon Seo , Roy B. Silverstein
IPC分类号： H03K17/16
CPC分类号： H04L25/0278
摘要： A buffer amplifier has a power on state and a sleep state. During regular operation a coupling state of a load to an output node is detected using feedback voltage. In a sleep mode and in a power collapse mode a detection current is injected into the output node, to produce a voltage, and the coupling state of the load is detected from the voltage. Optionally, the detection current and detecting of the voltage on the output node is enables by a low duty cycle clock. Optionally, signals generated in detecting the coupling state are qualified through a debounce circuit.
摘要翻译：缓冲放大器具有通电状态和睡眠状态。在正常操作期间，使用反馈电压来检测负载到输出节点的耦合状态。在睡眠模式和功率崩溃模式中，检测电流被注入到输出节点中以产生电压，并且从电压检测负载的耦合状态。可选地，通过低占空比时钟启用检测电流和输出节点上的电压检测。可选地，通过去抖动电路来限定在检测耦合状态时产生的信号。

2. 发明申请

US20100295581A1 BUFFER WITH ACTIVE OUTPUT IMPEDANCE MATCHING 有权
标题翻译：具有主动输出阻抗匹配的缓冲器
公开(公告)号：US20100295581A1
公开(公告)日：2010-11-25
申请号：US12604186
申请日：2009-10-22
申请人： Shahin Mehdizad Taleie , Jan Paul van der Wagt
发明人： Shahin Mehdizad Taleie , Jan Paul van der Wagt
IPC分类号： H03B1/00
CPC分类号： H03F1/223 , H03F1/56 , H03F3/72 , H03F2200/387 , H03F2200/453 , H03F2200/456 , H03F2200/513 , H03F2203/7236 , H03H11/30 , H04L25/0278 , H04L25/028
摘要： Techniques for designing a buffer capable of working with low supply voltages, and having active output impedance matching capability to optimize power delivery to a wide range of loads. In an exemplary embodiment, cascode transistors are provided in a buffer architecture employing common-source transistors having unequal width-to-length ratios (W/L) and a resistance having a corresponding fixed ratio to the load. At least one of the cascode transistors may be dynamically biased to minimize a difference between the drain voltages of the common-source transistors. In a further exemplary embodiment, the output impedance of the buffer may be actively tuned by selectively enabling a set of tuning transistors coupled in parallel with the load. Further techniques for providing a calibration mode and an operation mode are described.
摘要翻译：用于设计能够处理低电源电压的缓冲器的技术，并且具有有源输出阻抗匹配能力以优化向广泛负载的功率传递。在示例性实施例中，共源共栅晶体管被提供在采用具有不等宽/长比（W / L）和具有与负载相对应的固定比率的电阻的公共源晶体管的缓冲结构中。可以动态地偏置共源共栅晶体管中的至少一个以最小化共源极晶体管的漏极电压之间的差。在另一示例性实施例中，可以通过选择性地使能与负载并联耦合的一组调谐晶体管来主动调谐缓冲器的输出阻抗。描述了用于提供校准模式和操作模式的其它技术。

3. 发明授权

US08410824B2 Buffer with active output impedance matching 有权
标题翻译：具有有源输出阻抗匹配的缓冲器
公开(公告)号：US08410824B2
公开(公告)日：2013-04-02
申请号：US12604186
申请日：2009-10-22
申请人： Shahin Mehdizad Taleie , Jan Paul van der Wagt
发明人： Shahin Mehdizad Taleie , Jan Paul van der Wagt
IPC分类号： H03K3/00
CPC分类号： H03F1/223 , H03F1/56 , H03F3/72 , H03F2200/387 , H03F2200/453 , H03F2200/456 , H03F2200/513 , H03F2203/7236 , H03H11/30 , H04L25/0278 , H04L25/028
摘要： Techniques for designing a buffer capable of working with low supply voltages, and having active output impedance matching capability to optimize power delivery to a wide range of loads. In an exemplary embodiment, cascode transistors are provided in a buffer architecture employing common-source transistors having unequal width-to-length ratios (W/L) and a resistance having a corresponding fixed ratio to the load. At least one of the cascode transistors may be dynamically biased to minimize a difference between the drain voltages of the common-source transistors. In a further exemplary embodiment, the output impedance of the buffer may be actively tuned by selectively enabling a set of tuning transistors coupled in parallel with the load. Further techniques for providing a calibration mode and an operation mode are described.
摘要翻译：用于设计能够处理低电源电压的缓冲器的技术，并且具有有源输出阻抗匹配能力以优化向广泛负载的功率传递。在示例性实施例中，共源共栅晶体管被提供在采用具有不等宽/长比（W / L）和具有与负载相对应的固定比率的电阻的公共源晶体管的缓冲结构中。可以动态地偏置共源共栅晶体管中的至少一个以最小化共源极晶体管的漏极电压之间的差。在另一示例性实施例中，可以通过选择性地使能与负载并联耦合的一组调谐晶体管来主动调谐缓冲器的输出阻抗。描述了用于提供校准模式和操作模式的其它技术。

4. 发明申请

US20130076436A1 LOAD DETECTING IMPEDANCE MATCHING BUFFER 有权
标题翻译：负载检测阻抗匹配缓冲器
公开(公告)号：US20130076436A1
公开(公告)日：2013-03-28
申请号：US13241516
申请日：2011-09-23
申请人： Liviu Chiaburu , Shahin Mehdizad Taleie , Dongwon Seo , Roy Silverstein
发明人： Liviu Chiaburu , Shahin Mehdizad Taleie , Dongwon Seo , Roy Silverstein
IPC分类号： H03F1/00
CPC分类号： H04L25/0278
摘要： A buffer amplifier has a power on state and a sleep state. During regular operation a coupling state of a load to an output node is detected using feedback voltage. In a sleep mode and in a power collapse mode a detection current is injected into the output node, to produce a voltage, and the coupling state of the load is detected from the voltage. Optionally, the detection current and detecting of the voltage on the output node is enables by a low duty cycle clock. Optionally, signals generated in detecting the coupling state are qualified through a debounce circuit.
摘要翻译：缓冲放大器具有通电状态和睡眠状态。在正常操作期间，使用反馈电压来检测负载到输出节点的耦合状态。在睡眠模式和功率崩溃模式中，检测电流被注入到输出节点中以产生电压，并且从电压检测负载的耦合状态。可选地，通过低占空比时钟启用检测电流和输出节点上的电压检测。可选地，通过去抖动电路来限定在检测耦合状态时产生的信号。

5. 发明授权

US08169353B2 Wideband digital to analog converter with built-in load attenuator 有权
标题翻译：宽带数模转换器，内置负载衰减器
公开(公告)号：US08169353B2
公开(公告)日：2012-05-01
申请号：US12686998
申请日：2010-01-13
申请人： Dongwon Seo , Ganesh R Saripalli , Tongyu Song , Shahin Mehdizad Taleie , Derui Kong
发明人： Dongwon Seo , Ganesh R Saripalli , Tongyu Song , Shahin Mehdizad Taleie , Derui Kong
IPC分类号： H03M1/66
CPC分类号： H03M1/742 , H03F1/223 , H03F1/3241 , H03F3/195 , H03F3/245 , H03F3/45183
摘要： A circuit for digital-to-analog conversion is described. The circuit includes a digital-to-analog converter (DAC). The DAC includes a double cascaded current source and a differential current-mode switch (DCMS). The circuit further includes a direct current (DC) offset stage. The circuit also includes a load attenuator. The double cascaded current source may be between the DCMS and a rail voltage.
摘要翻译：描述用于数模转换的电路。该电路包括一个数模转换器（DAC）。 DAC包括双级联电流源和差分电流模式开关（DCMS）。电路还包括直流（DC）偏置级。该电路还包括负载衰减器。双级联电流源可以在DCMS和轨道电压之间。

6. 发明授权

US08638165B2 Switched-capacitor DC blocking amplifier 有权
标题翻译：开关电容直流阻塞放大器
公开(公告)号：US08638165B2
公开(公告)日：2014-01-28
申请号：US13271130
申请日：2011-10-11
申请人： Peter J Shah , Shahin Mehdizad Taleie , Gerrit Groenewold , Guoqing Miao , Eunyung Sung
发明人： Peter J Shah , Shahin Mehdizad Taleie , Gerrit Groenewold , Guoqing Miao , Eunyung Sung
IPC分类号： H03F1/02
CPC分类号： H03F3/45475 , H03F3/005 , H03F2200/03 , H03F2200/552 , H03F2203/45512 , H03F2203/45514 , H03F2203/45528 , H03F2203/45594 , H03F2203/45631
摘要： A switched-capacitor DC blocking amplifier is disclosed. In an embodiment, an integrated circuit is provided that includes an amplifier having an amplifier input and an amplifier output, a capacitor connected to the amplifier input and configured to receive an input signal, and a switched capacitor circuit coupled to provide a resistance between the amplifier input and the amplifier output. In one implementation, the switched capacitor circuit is configured with a feed forward circuit to reduce aliasing. In another implementation, the switched capacitor circuit includes a switched impedance circuit to reduce noise.
摘要翻译：公开了一种开关电容器直流阻塞放大器。在一个实施例中，提供一种集成电路，其包括具有放大器输入和放大器输出的放大器，连接到放大器输入并被配置为接收输入信号的电容器，以及耦合以提供放大器之间的电阻的开关电容器电路输入和放大器输出。在一个实现中，开关电容器电路配置有前馈电路以减少混叠。在另一实施方案中，开关电容器电路包括用于降低噪声的开关阻抗电路。

7. 发明申请

US20120306575A1 SWITCHED-CAPACITOR DC BLOCKING AMPLIFIER 有权
标题翻译：开关电容直流阻塞放大器
公开(公告)号：US20120306575A1
公开(公告)日：2012-12-06
申请号：US13271130
申请日：2011-10-11
申请人： Peter J. Shah , Shahin Mehdizad Taleie , Gerrit Groenewold , Guoqing Miao , Eunyung Sung
发明人： Peter J. Shah , Shahin Mehdizad Taleie , Gerrit Groenewold , Guoqing Miao , Eunyung Sung
IPC分类号： H03F3/45 , H03F1/34
CPC分类号： H03F3/45475 , H03F3/005 , H03F2200/03 , H03F2200/552 , H03F2203/45512 , H03F2203/45514 , H03F2203/45528 , H03F2203/45594 , H03F2203/45631
摘要： A switched-capacitor DC blocking amplifier is disclosed. In an embodiment, an integrated circuit is provided that includes an amplifier having an amplifier input and an amplifier output, a capacitor connected to the amplifier input and configured to receive an input signal, and a switched capacitor circuit coupled to provide a resistance between the amplifier input and the amplifier output. In one implementation, the switched capacitor circuit is configured with a feed forward circuit to reduce aliasing. In another implementation, the switched capacitor circuit includes a switched impedance circuit to reduce noise.
摘要翻译：公开了一种开关电容器直流阻塞放大器。在一个实施例中，提供一种集成电路，其包括具有放大器输入和放大器输出的放大器，连接到放大器输入并被配置为接收输入信号的电容器，以及耦合以提供放大器之间的电阻的开关电容器电路输入和放大器输出。在一个实现中，开关电容器电路配置有前馈电路以减少混叠。在另一实施方案中，开关电容器电路包括用于降低噪声的开关阻抗电路。

8. 发明申请

US20110074615A1 WIDEBAND DIGITAL TO ANALOG CONVERTER WITH BUILT-IN LOAD ATTENUATOR 有权
标题翻译：宽带数字到模拟转换器与内置负载衰减器
公开(公告)号：US20110074615A1
公开(公告)日：2011-03-31
申请号：US12686998
申请日：2010-01-13
申请人： Dongwon Seo , Ganesh R. Saripalli , Tongyu Song , Shahin Mehdizad Taleie , Derui Kong
发明人： Dongwon Seo , Ganesh R. Saripalli , Tongyu Song , Shahin Mehdizad Taleie , Derui Kong
IPC分类号： H03M1/66
CPC分类号： H03M1/742 , H03F1/223 , H03F1/3241 , H03F3/195 , H03F3/245 , H03F3/45183
摘要： A circuit for digital-to-analog conversion is described. The circuit includes a digital-to-analog converter (DAC). The DAC includes a double cascaded current source and a differential current-mode switch (DCMS). The circuit further includes a direct current (DC) offset stage. The circuit also includes a load attenuator. The double cascaded current source may be between the DCMS and a rail voltage.
摘要翻译：描述用于数模转换的电路。该电路包括一个数模转换器（DAC）。 DAC包括双级联电流源和差分电流模式开关（DCMS）。电路还包括直流（DC）偏置级。该电路还包括负载衰减器。双级联电流源可以在DCMS和轨道电压之间。

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