专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20160005852A1 SEMICONDUCTOR DEVICES HAVING LOWER AND UPPER FINS AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：具有下层和上层FINS的半导体器件及其制造方法
公开(公告)号：US20160005852A1
公开(公告)日：2016-01-07
申请号：US14690575
申请日：2015-04-20
申请人： Sung-Min Kim , Kyung-Seok Oh , Cheol Kim , Heon-Jong Shin , Jong-Ryeol Yoo , Hyun-Jung Lee , Seong-Hoon Jeong
发明人： Sung-Min Kim , Kyung-Seok Oh , Cheol Kim , Heon-Jong Shin , Jong-Ryeol Yoo , Hyun-Jung Lee , Seong-Hoon Jeong
IPC分类号： H01L29/78 , H01L29/40 , H01L29/06
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/42392 , H01L29/66795
摘要： Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a lower fin that protrudes from a substrate and extends in a first direction, an oxide film the lower fin, an upper fin that protrudes from the oxide film and that is spaced apart from the lower fin at a position corresponding to the lower fin, and a gate structure the upper fin that extends in a second direction to intersect the upper fin, wherein germanium (Ge) is included in a portion of the oxide film located between the lower fin and the upper fin.
摘要翻译：提供一种半导体器件及其制造方法。半导体器件包括从基板突出并沿第一方向延伸的下翅片，下鳍片上的氧化膜，从氧化膜突出并与下翅片间隔开的上翅片，下翅片和栅极结构，上翅片沿第二方向延伸以与上翅片相交，其中锗（Ge）包括在位于下翅片和上翅片之间的氧化膜的一部分中。

2. 再颁专利

USRE44564E1 Method for transmitting control signal using efficient multiplexing 有权
标题翻译：使用高效复用发送控制信号的方法
公开(公告)号：USRE44564E1
公开(公告)日：2013-10-29
申请号：US13476973
申请日：2012-05-21
申请人： Hak Seong Kim , Sung Duk Choi , Ki Jun Kim , Suk Hyon Yoon , Joon Kui Ahn , Bong Hoe Kim , Dong Youn Seo , Young Woo Yun , Jung Hoon Lee , Seong Hoon Jeong
发明人： Hak Seong Kim , Sung Duk Choi , Ki Jun Kim , Suk Hyon Yoon , Joon Kui Ahn , Bong Hoe Kim , Dong Youn Seo , Young Woo Yun , Jung Hoon Lee , Seong Hoon Jeong
IPC分类号： H04B7/216
摘要： Methods of transmitting a control signal using efficient multiplexing are disclosed. One of the method includes the steps of multiplexing a plurality of 1-bit control signals within a prescribed time-frequency domain by code division multiple access (CDMA) and transmitting the multiplexed control signals, wherein a plurality of the 1-bit control signals include a plurality of the 1-bit control signals for a specific transmitting side. Accordingly, reliability on 1-bit control signal transmission can be enhanced.
摘要翻译：公开了使用高效复用来发送控制信号的方法。该方法之一包括以下步骤：通过码分多址（CDMA）在规定的时频域内复用多个1位控制信号，并发送多路复用控制信号，其中多个1位控制信号包括用于特定发送侧的多个1位控制信号。因此，可以提高1位控制信号传输的可靠性。

3. 发明授权

US08509175B2 Method for transmitting downlink control signal 有权
标题翻译：发送下行控制信号的方法
公开(公告)号：US08509175B2
公开(公告)日：2013-08-13
申请号：US13217204
申请日：2011-08-24
申请人： Hak Seong Kim , Sung Duk Choi , Ki Jun Kim , Suk Hyon Yoon , Joon Kui Ahn , Bong Hoe Kim , Dong Youn Seo , Young Woo Yun , Seong Hoon Jeong , Eun Sun Kim , Dae Won Lee , Jung Hoon Lee
发明人： Hak Seong Kim , Sung Duk Choi , Ki Jun Kim , Suk Hyon Yoon , Joon Kui Ahn , Bong Hoe Kim , Dong Youn Seo , Young Woo Yun , Seong Hoon Jeong , Eun Sun Kim , Dae Won Lee , Jung Hoon Lee
IPC分类号： H04W4/00
CPC分类号： H04L1/0027 , H04L5/005 , H04L5/0051 , H04L5/0053 , H04L27/261 , H04W72/14
摘要： A method of transmitting a downlink control signal is disclosed, by which localized allocation and distributed allocation are efficiently used in transmitting a downlink control signal. The present invention includes multiplexing the downlink control signal in a manner of if there exists downlink data transmission to a prescribed UE, applying localized allocation to a transmission of the downlink control signal including the scheduling information on the uplink data transmission of the UE and applying distributed allocation to another transmission of the downlink control signal and transmitting the multiplexed downlink control signal.
摘要翻译：公开了一种发送下行链路控制信号的方法，通过该方法，在发送下行链路控制信号中有效地使用集中分配和分布式分配。本发明包括以下述方式对下行链路控制信号进行多路复用：如果存在向规定的UE的下行链路数据传输，对包括关于UE的上行链路数据传输的调度信息的下行链路控制信号的发送应用集中分配，分配给下行链路控制信号的另一个传输，并发送多路复用的下行链路控制信号。

4. 发明申请

US20120282769A1 METHODS OF FORMING INTEGRATED CIRCUIT DEVICES HAVING ELECTRICALLY CONDUCTIVE LAYERS THEREIN WITH PARTIALLY NITRIDATED SIDEWALLS 有权
标题翻译：形成具有部分硝化面的电导体层的集成电路装置的方法
公开(公告)号：US20120282769A1
公开(公告)日：2012-11-08
申请号：US13551251
申请日：2012-07-17
申请人： Jeong-Do Ryu , Si-Young CHOI , Yu-Gyun SHIN , Tai-Su PARK , Dong-Chan KIM , Jong-Ryeol YOO , Seong-Hoon JEONG , Jong-Hoon KANG
发明人： Jeong-Do Ryu , Si-Young CHOI , Yu-Gyun SHIN , Tai-Su PARK , Dong-Chan KIM , Jong-Ryeol YOO , Seong-Hoon JEONG , Jong-Hoon KANG
IPC分类号： H01L21/28
CPC分类号： H01L21/28061 , H01L21/28247 , H01L21/3211 , H01L21/32137 , H01L21/32139 , H01L27/10873 , H01L27/11 , H01L27/1104
摘要： Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.
摘要翻译：形成集成电路器件的方法包括在衬底上形成含硅的导电层，并在导电层上形成掩模图案。使用掩模图案作为蚀刻掩模，选择性地蚀刻导电层以限定其上的第一侧壁。可以将导电层的第一侧壁暴露于氮等离子体，从而在第一侧壁上形成第一氮化硅层。然后再次选择性地蚀刻导电层以暴露其上没有第一氮化硅层的第二侧壁。在选择性蚀刻导电层的第二步骤期间，掩模图案可以再次用作蚀刻掩模。

5. 外观设计

USD662107S1 Digital television with a graphical user interface 有权
标题翻译：具有图形用户界面的数字电视
公开(公告)号：USD662107S1
公开(公告)日：2012-06-19
申请号：US29371135
申请日：2010-10-29
申请人： Jeong-Yeon Lee , Heui-Jin Kwon , Woo-Seok Hwang , Seong-Hoon Jeong
设计人： Jeong-Yeon Lee , Heui-Jin Kwon , Woo-Seok Hwang , Seong-Hoon Jeong

6. 发明授权

US07953061B2 Method for transmitting control signal using efficient multiplexing 有权
标题翻译：使用高效复用发送控制信号的方法
公开(公告)号：US07953061B2
公开(公告)日：2011-05-31
申请号：US12444100
申请日：2007-10-02
申请人： Hak Seong Kim , Sung Duk Choi , Ki Jun Kim , Suk Hyon Yoon , Joon Kui Ahn , Bong Hoe Kim , Dong Youn Seo , Young Woo Yun , Jung Hoon Lee , Seong Hoon Jeong
发明人： Hak Seong Kim , Sung Duk Choi , Ki Jun Kim , Suk Hyon Yoon , Joon Kui Ahn , Bong Hoe Kim , Dong Youn Seo , Young Woo Yun , Jung Hoon Lee , Seong Hoon Jeong
IPC分类号： H04B7/216
CPC分类号： H04L5/0007 , H04L1/1607 , H04L1/1854 , H04L1/1858 , H04L1/1861 , H04L5/0026 , H04L5/0053 , H04L5/0055 , H04W72/0446 , H04W72/0453 , H04W88/02 , H04W88/08
摘要： Methods of transmitting a control signal using efficient multiplexing are disclosed. One of the method includes the steps of multiplexing a plurality of 1-bit control signals within a prescribed time-frequency domain by code division multiple access (CDMA) and transmitting the multiplexed control signals, wherein a plurality of the 1-bit control signals include a plurality of the 1-bit control signals for a specific transmitting side. Accordingly, reliability on 1-bit control signal transmission can be enhanced.
摘要翻译：公开了使用高效复用来发送控制信号的方法。该方法之一包括以下步骤：通过码分多址（CDMA）在规定的时频域内复用多个1位控制信号，并发送多路复用控制信号，其中多个1位控制信号包括用于特定发送侧的多个1位控制信号。因此，可以提高1位控制信号传输的可靠性。

7. 发明申请

US20100072545A1 Recessed Channel Array Transistors, and Semiconductor Devices Including a Recessed Channel Array Transistor 有权
标题翻译：嵌入式通道阵列晶体管和包括嵌入式通道阵列晶体管的半导体器件
公开(公告)号：US20100072545A1
公开(公告)日：2010-03-25
申请号：US12563473
申请日：2009-09-21
申请人： Jeong-Do Ryu , Dong-Chan Kim , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin , Tai-Su Park , Jong-Ryeol Yoo , Jong-Hoon Kang
发明人： Jeong-Do Ryu , Dong-Chan Kim , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin , Tai-Su Park , Jong-Ryeol Yoo , Jong-Hoon Kang
IPC分类号： H01L27/06 , H01L29/78
CPC分类号： H01L29/66795 , H01L21/28211 , H01L21/823412 , H01L27/105 , H01L27/10876 , H01L27/10879 , H01L27/10894 , H01L27/11 , H01L29/4236 , H01L29/51 , H01L29/66621 , H01L29/7851
摘要： A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current.
摘要翻译：凹陷通道阵列晶体管可以包括衬底，栅极氧化物层，栅极电极和源极/漏极区域。衬底可以具有有源区和隔离区。可以在活性区域中形成凹陷。栅极氧化物层可以形成在凹部和基板上。栅极氧化物层可以包括在凹部的侧端和有源区的侧壁与凹部的侧表面上的第二部分之间的交叉处的第一部分。第一部分可以包括大于第二部分厚度的约70％的厚度。栅极电极可以形成在栅极氧化物层上。源极/漏极区域可以形成在衬底中。因此，凹陷通道阵列晶体管可能具有减小的漏电流和增加的导通电流。

8. 发明授权

US6115172A Thin film actuated mirror array 失效
标题翻译：薄膜致动反射镜阵列
公开(公告)号：US6115172A
公开(公告)日：2000-09-05
申请号：US106845
申请日：1998-06-30
申请人： Seong-Hoon Jeong
发明人： Seong-Hoon Jeong
IPC分类号： G02B26/08 , G09F9/37 , H01L49/00 , G02B26/00
CPC分类号： G02B26/0841 , G02B26/0833
摘要： Thin film AMA is disclosed. The thin film AMA has an active matrix, a supporting member, an actuator, and a reflecting member. The actuator has a bottom electrode, two active layers, and two top electrodes. The actuator has maximum tilting angle due to margins formed between the bottom electrode and the two active layers or between the two active layers and the two top electrodes. Also, the tilting angle of the actuator is increased because the layers of the actuator respectively have proper thicknesses. Therefore, the quality of the picture projected onto a screen is enhanced and the arrangement of the AMA may be more easy.
摘要翻译：公开了薄膜AMA。薄膜AMA具有有源矩阵，支撑构件，致动器和反射构件。致动器具有底部电极，两个有源层和两个顶部电极。由于在底部电极和两个有源层之间或两个有源层和两个顶部电极之间形成的边缘，致动器具有最大倾斜角。此外，致动器的倾斜角度增加，因为致动器的层分别具有适当的厚度。因此，投影到屏幕上的图像的质量得到提高，并且AMA的布置可能更容易。

9. 发明授权

US09190495B2 Recessed channel array transistors, and semiconductor devices including a recessed channel array transistor 有权
标题翻译：嵌入式沟道阵列晶体管和包括凹陷沟道阵列晶体管的半导体器件
公开(公告)号：US09190495B2
公开(公告)日：2015-11-17
申请号：US12563473
申请日：2009-09-21
申请人： Jeong-Do Ryu , Dong-Chan Kim , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin , Tai-Su Park , Jong-Ryeol Yoo , Jong-Hoon Kang
发明人： Jeong-Do Ryu , Dong-Chan Kim , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin , Tai-Su Park , Jong-Ryeol Yoo , Jong-Hoon Kang
IPC分类号： H01L27/06 , H01L29/78 , H01L29/66 , H01L21/28 , H01L27/105 , H01L27/108 , H01L27/11 , H01L29/423 , H01L29/51 , H01L21/336 , H01L21/8234
CPC分类号： H01L29/66795 , H01L21/28211 , H01L21/823412 , H01L27/105 , H01L27/10876 , H01L27/10879 , H01L27/10894 , H01L27/11 , H01L29/4236 , H01L29/51 , H01L29/66621 , H01L29/7851
摘要： A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current.
摘要翻译：凹陷通道阵列晶体管可以包括衬底，栅极氧化物层，栅极电极和源极/漏极区域。衬底可以具有有源区和隔离区。可以在活性区域中形成凹部。栅极氧化物层可以形成在凹部和基板上。栅极氧化物层可以包括在凹部的侧端和有源区的侧壁与凹部的侧表面上的第二部分之间的交叉处的第一部分。第一部分可以包括大于第二部分厚度的约70％的厚度。栅极电极可以形成在栅极氧化物层上。源极/漏极区域可以形成在衬底中。因此，凹陷通道阵列晶体管可能具有减小的漏电流和增加的导通电流。

10. 发明授权

US08319260B2 Semiconductor devices having polysilicon gate layer patterns and methods of manufacturing the same 有权
标题翻译：具有多晶硅栅极层图案的半导体器件及其制造方法
公开(公告)号：US08319260B2
公开(公告)日：2012-11-27
申请号：US12805400
申请日：2010-07-29
申请人： Deok-Hyung Lee , Soo-Jin Hong , Seong-Hoon Jeong
发明人： Deok-Hyung Lee , Soo-Jin Hong , Seong-Hoon Jeong
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/823842 , H01L29/7845
摘要： In semiconductor devices, methods of forming the same, the semiconductor device include a first gate structure having a first gate oxide layer pattern, a first polysilicon layer pattern containing atoms larger than silicon and a first hard mask layer pattern on substrates under tensile stress. N-type impurity regions are formed under the surface of the substrate on both sides of the first gate structure. A second gate structure having a second gate oxide layer pattern, a second polysilicon layer pattern containing atoms smaller than silicon and a second hard mask layer pattern on substrates under compressive stress. Additionally, P-type impurity regions are formed under the surface of the substrate on both sides of the second gate structure. The semiconductor devices have good device properties.
摘要翻译：在半导体器件中，形成半导体器件的方法包括具有第一栅极氧化层图案的第一栅极结构，包含比硅大的原子的第一多晶硅层图案和在拉伸应力下的基板上的第一硬掩模层图案。在第一栅极结构的两侧的衬底的表面下方形成N型杂质区。具有第二栅极氧化物层图案的第二栅极结构，在压缩应力下在基底上含有小于硅的原子的第二多晶硅层图案和第二硬掩模层图案。此外，在第二栅极结构的两侧在基板的表面下方形成P型杂质区。半导体器件具有良好的器件特性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式