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1. 发明授权

US08051346B2 Fault injection 有权
标题翻译：故障注入
公开(公告)号：US08051346B2
公开(公告)日：2011-11-01
申请号：US12392468
申请日：2009-02-25
申请人： Senthil Somasundaram , Jun Qian , Paul Chang , Thomas A. Hamilton
发明人： Senthil Somasundaram , Jun Qian , Paul Chang , Thomas A. Hamilton
IPC分类号： G01R31/28 , G01R31/08 , G01R27/28 , G01R31/00 , G01R31/14 , G11C7/00 , G11C29/00
CPC分类号： G01R31/31716 , G01R31/31706 , G01R31/31717
摘要： Systems, methods, and other embodiments associated with programmable application specific integrated circuit (ASIC) fault injection are described. One example ASIC includes a serializer de-serializer (SERDES). The example ASIC may also include logics to process data in the ASIC. At least one of the logics either receives data from the SERDES and/or provides data to the SERDES. The example ASIC may also include an embedded fault injection logic (EFIL) to control injection of a fault to a path (e.g., data, control) associated with at least one of the logics. The example ASIC may also include an embedded set of multiplexers (ESOMs) controlled by the EFIL. The ESOMs are controllable by the EFIL to inject a fault signal to the data path.
摘要翻译：描述了与可编程应用专用集成电路（ASIC）故障注入相关联的系统，方法和其他实施例。一个示例性ASIC包括串行器解串器（SERDES）。示例ASIC还可以包括用于处理ASIC中的数据的逻辑。至少有一个逻辑可以从SERDES接收数据和/或向SERDES提供数据。示例性ASIC还可以包括嵌入式故障注入逻辑（EFIL），以控制将故障注入与至少一个逻辑相关联的路径（例如，数据，控制）。示例性ASIC还可以包括由EFIL控制的嵌入式多路复用器集合（ESOM）。 ESOM可由EFIL控制，以将故障信号注入数据通路。

2. 发明申请

US20100218058A1 FAULT INJECTION 有权
标题翻译：故障注意
公开(公告)号：US20100218058A1
公开(公告)日：2010-08-26
申请号：US12392468
申请日：2009-02-25
申请人： Senthil SOMASUNDARAM , Jun QIAN , Paul CHANG , Thomas A. HAMILTON
发明人： Senthil SOMASUNDARAM , Jun QIAN , Paul CHANG , Thomas A. HAMILTON
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31716 , G01R31/31706 , G01R31/31717
摘要： Systems, methods, and other embodiments associated with programmable application specific integrated circuit (ASIC) fault injection are described. One example ASIC includes a serializer de-serializer (SERDES). The example ASIC may also include logics to process data in the ASIC. At least one of the logics either receives data from the SERDES and/or provides data to the SERDES. The example ASIC may also include an embedded fault injection logic (EFIL) to control injection of a fault to a path (e.g., data, control) associated with at least one of the logics. The example ASIC may also include an embedded set of multiplexers (ESOMs) controlled by the EFIL. The ESOMs are controllable by the EFIL to inject a fault signal to the data path.
摘要翻译：描述了与可编程应用专用集成电路（ASIC）故障注入相关联的系统，方法和其他实施例。一个示例性ASIC包括串行器解串器（SERDES）。示例ASIC还可以包括用于处理ASIC中的数据的逻辑。至少有一个逻辑可以从SERDES接收数据和/或向SERDES提供数据。示例性ASIC还可以包括嵌入式故障注入逻辑（EFIL），以控制将故障注入与至少一个逻辑相关联的路径（例如，数据，控制）。示例性ASIC还可以包括由EFIL控制的嵌入式多路复用器集合（ESOM）。 ESOM可由EFIL控制，以将故障信号注入数据通路。

3. 发明授权

US07908533B2 Processor to JTAG test access port interface 有权
标题翻译：处理器到JTAG测试访问端口接口
公开(公告)号：US07908533B2
公开(公告)日：2011-03-15
申请号：US12203109
申请日：2008-09-02
申请人： Senthil Somasundaram , Jun Qian
发明人： Senthil Somasundaram , Jun Qian
IPC分类号： G01R31/28
CPC分类号： G06F11/267 , G01R31/318533 , G01R31/318555
摘要： Method and apparatus for operating for operating an Institute of Electrical and Electronics Engineers (IEEE) Standard 1149.1 compliant Joint Test Action Group (JTAG) Test Access Port (TAP) controller are disclosed. An example apparatus includes write logic that is configured to operationally interface with a TAP controller and a processor. The write logic is further configured to receive, from the processor, data for initializing the apparatus and operating the TAP controller, convert at least a portion of the data from a parallel format to a serial format and communicate the converted data to the TAP controller.
摘要翻译：公开了用于操作电气和电子工程师协会（IEEE）标准1149.1兼容联合测试行动组（JTAG）测试访问端口（TAP）控制器的方法和装置。一种示例性装置包括被配置为与TAP控制器和处理器操作地接口的写入逻辑。写逻辑还被配置为从处理器接收用于初始化装置和操作TAP控制器的数据，将来自并行格式的数据的至少一部分转换为串行格式，并将转换后的数据传送给TAP控制器。

4. 发明申请

US20100090743A1 INTERFACE TO REGULATE VOLTAGE FOR ASIC POWER MANAGEMENT 有权
标题翻译：用于ASIC电源管理的界面来调节电压
公开(公告)号：US20100090743A1
公开(公告)日：2010-04-15
申请号：US12249589
申请日：2008-10-10
申请人： Mehran Ataee , Udupi Harisharan , Jun Qian , Thomas A. Hamilton , Senthil Somasundaram
发明人： Mehran Ataee , Udupi Harisharan , Jun Qian , Thomas A. Hamilton , Senthil Somasundaram
IPC分类号： H03L5/00
CPC分类号： H03K19/00369
摘要： A method and apparatus to regulate voltage used to power an ASIC comprising an ASIC having a signal source and a modulator. The modulator establishes a characteristic of a signal created by the signal source to indicate a voltage level to be used to power the ASIC. The signal is communicated to a voltage regulator to apply an optimal voltage to the ASIC.
摘要翻译：一种用于调节用于为包含具有信号源和调制器的ASIC的ASIC供电的电压的方法和装置。调制器建立由信号源产生的信号的特性，以指示要用于为ASIC供电的电压电平。该信号被传送到电压调节器以向ASIC施加最佳电压。

5. 发明申请

US20100058130A1 PROCESSOR TO JTAG TEST ACCESS PORT INTERFACE 有权
标题翻译：处理器到JTAG测试访问端口接口
公开(公告)号：US20100058130A1
公开(公告)日：2010-03-04
申请号：US12203109
申请日：2008-09-02
申请人： Senthil Somasundaram , Jun Qian
发明人： Senthil Somasundaram , Jun Qian
IPC分类号： G01R31/3177 , G06F11/27
CPC分类号： G06F11/267 , G01R31/318533 , G01R31/318555
摘要： Method and apparatus for operating for operating an Institute of Electrical and Electronics Engineers (IEEE) Standard 1149.1 compliant Joint Test Action Group (JTAG) Test Access Port (TAP) controller are disclosed. An example apparatus includes write logic that is configured to operationally interface with a TAP controller and a processor. The write logic is further configured to receive, from the processor, data for initializing the apparatus and operating the TAP controller, convert at least a portion of the data from a parallel format to a serial format and communicate the converted data to the TAP controller.
摘要翻译：公开了用于操作电气和电子工程师协会（IEEE）标准1149.1兼容联合测试行动组（JTAG）测试访问端口（TAP）控制器的方法和装置。一种示例性装置包括被配置为与TAP控制器和处理器操作地接口的写入逻辑。写逻辑还被配置为从处理器接收用于初始化装置和操作TAP控制器的数据，将来自并行格式的数据的至少一部分转换为串行格式，并将转换后的数据传送给TAP控制器。

6. 发明授权

US08264210B2 Interface to regulate voltage for ASIC power management 有权
标题翻译：用于ASIC电源管理的电压调节接口
公开(公告)号：US08264210B2
公开(公告)日：2012-09-11
申请号：US12249589
申请日：2008-10-10
申请人： Mehran Ataee , Udupi Harisharan , Jun Qian , Thomas A. Hamilton , Senthil Somasundaram
发明人： Mehran Ataee , Udupi Harisharan , Jun Qian , Thomas A. Hamilton , Senthil Somasundaram
IPC分类号： G05F1/00 , H03L5/00
CPC分类号： H03K19/00369
摘要： A method and apparatus to regulate voltage used to power an ASIC comprising an ASIC having a signal source and a modulator. The modulator establishes a characteristic of a signal created by the signal source to indicate a voltage level to be used to power the ASIC. The signal is communicated to a voltage regulator to apply an optimal voltage to the ASIC.
摘要翻译：一种用于调节用于为包含具有信号源和调制器的ASIC的ASIC供电的电压的方法和装置。调制器建立由信号源产生的信号的特性，以指示要用于为ASIC供电的电压电平。该信号被传送到电压调节器以向ASIC施加最佳电压。

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