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    • 4. 发明授权
    • Method of manufacturing an insulated gate field effect transistor
    • 绝缘栅场效应晶体管的制造方法
    • US4610076A
    • 1986-09-09
    • US655672
    • 1984-09-28
    • Seiji Ueda
    • Seiji Ueda
    • H01L23/52H01L21/28H01L21/3205H01L21/336H01L21/768H01L23/522H01L21/38
    • H01L29/6659
    • In a method of manufacturing a semiconductor device, a thin silicon dioxide (SiO.sub.2) film for a gate insulation film and a polycrystalline silicon layer are successively deposited on a semiconductor substrate having one electrical conductivity type whereby this polycrystalline silicon layer has a gate electrode pattern. In this step a part of the polycrystalline silicon layer is left at a part where an electric contact with the substrate is to be formed. Parts of source and drain regions are formed by the self-align method with this polycrystalline silicon layer as a mask. A thick passivation film for an interlayer insulation film is formed to cover the whole surface. An aperture is formed selectively in the passivation film to expose the whole polycrystalline silicon layer at the part where the contact is formed. The polycrystalline silicon layer in the aperture part and the thin insulation film thereunder are removed to expose a part of the semiconductor substrate. An impurity is introduced into this exposed part to form a contact region overlapped with a part of the above-mentioned source and drain regions. Therefore, the aperture part for a contact with source and drain regions can be formed without a step of mask adjustment. Thus, a highly integrated function device can be easily realized.
    • 在制造半导体器件的方法中,在具有一种导电类型的半导体衬底上依次沉积用于栅绝缘膜和多晶硅层的薄二氧化硅(SiO 2)膜,由此该多晶硅层具有栅电极图案。 在该步骤中,多晶硅层的一部分留在与基板形成电接触的部分。 源极和漏极区域的部分通过自对准方法形成,该多晶硅层作为掩模。 形成用于层间绝缘膜的厚钝化膜以覆盖整个表面。 在钝化膜中选择性地形成孔,以在形成接触的部分露出整个多晶硅层。 去除开口部分中的多晶硅层和其下的薄绝缘膜以暴露半导体衬底的一部分。 将杂质引入该暴露部分以形成与上述源极和漏极区域的一部分重叠的接触区域。 因此,可以在不进行掩模调节的步骤的情况下形成用于与源区和漏区接触的开口部。 因此,可以容易地实现高度集成的功能装置。