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1. 发明授权

US06893578B1 Selective etchant for oxide sacrificial material in semiconductor device fabrication 失效
标题翻译：半导体器件制造中氧化物牺牲材料的选择性蚀刻剂
公开(公告)号：US06893578B1
公开(公告)日：2005-05-17
申请号：US10010850
申请日：2001-12-05
申请人： Peggy J. Clews , Seethambal S. Mani
发明人： Peggy J. Clews , Seethambal S. Mani
IPC分类号： C03C15/00 , H01L21/311
CPC分类号： B81C1/00595 , C03C15/00 , H01L21/31111
摘要： An etching composition and method is disclosed for removing an oxide sacrificial material during manufacture of semiconductor devices including micromechanical, microelectromechanical or microfluidic devices. The etching composition and method are based on the combination of hydrofluoric acid (HF) and sulfuric acid (H2SO4). These acids can be used in the ratio of 1:3 to 3:1 HF:H2SO4 to remove all or part of the oxide sacrificial material while providing a high etch selectivity for non-oxide materials including polysilicon, silicon nitride and metals comprising aluminum. Both the HF and H2SO4 can be provided as “semiconductor grade” acids in concentrations of generally 40-50% by weight HF, and at least 90% by weight H2SO4.
摘要翻译：公开了用于在包括微机电，微机电或微流体装置的半导体器件的制造期间去除氧化物牺牲材料的蚀刻组合物和方法。蚀刻组合物和方法基于氢氟酸（HF）和硫酸（H 2 SO 3 SO 4）的组合。这些酸可以1:3至3:1的HF:H 2 SO 4的比例使用以除去全部或部分氧化物牺牲材料，同时提供高的包括多晶硅，氮化硅和包含铝的金属的非氧化物材料的蚀刻选择性。 HF和H 2 SO 4 H两者可以提供为浓度通常为40-50重量％HF和至少90重量％的浓度的“半导体级”酸 H 2 SO 4 4。

2. 发明授权

US08907439B1 Focal plane array with modular pixel array components for scalability 有权
标题翻译：具有模块化像素阵列组件的焦平面阵列，用于可扩展性
公开(公告)号：US08907439B1
公开(公告)日：2014-12-09
申请号：US13163909
申请日：2011-06-20
申请人： Randolph R. Kay , David V. Campbell , Subhash L. Shinde , Jeffrey L. Rienstra , Darwin K. Serkland , Michael L. Holmes , Seethambal S. Mani , Joy M. Barker , Dahwey Chu , Thomas Gurrieri
发明人： Randolph R. Kay , David V. Campbell , Subhash L. Shinde , Jeffrey L. Rienstra , Darwin K. Serkland , Michael L. Holmes , Seethambal S. Mani , Joy M. Barker , Dahwey Chu , Thomas Gurrieri
IPC分类号： H01L31/12
CPC分类号： H01L27/14634
摘要： A modular, scalable focal plane array is provided as an array of integrated circuit dice, wherein each die includes a given amount of modular pixel array circuitry. The array of dice effectively multiplies the amount of modular pixel array circuitry to produce a larger pixel array without increasing die size. Desired pixel pitch across the enlarged pixel array is preserved by forming die stacks with each pixel array circuitry die stacked on a separate die that contains the corresponding signal processing circuitry. Techniques for die stack interconnections and die stack placement are implemented to ensure that the desired pixel pitch is preserved across the enlarged pixel array.
摘要翻译：提供了一种模块化的，可缩放的焦平面阵列作为集成电路芯片的阵列，其中每个管芯包括给定量的模块化像素阵列电路。骰子阵列有效地将模块化像素阵列电路的数量乘以产生更大的像素阵列而不增加管芯尺寸。通过将每个像素阵列电路管芯堆叠在包含对应的信号处理电路的单独的管芯上形成管芯堆叠来保留扩大的像素阵列上期望的像素间距。实现用于管芯堆叠互连和管芯堆叠放置的技术以确保跨越扩大的像素阵列保留期望的像素间距。

3. 发明授权

US06808952B1 Process for fabricating a microelectromechanical structure 失效
标题翻译：制造微机电结构的方法
公开(公告)号：US06808952B1
公开(公告)日：2004-10-26
申请号：US10236631
申请日：2002-09-05
申请人： Jeffry J. Sniegowski , Thomas W. Krygowski , Seethambal S. Mani , Scott D. Habermehl , Dale L. Hetherington , James E. Stevens , Paul J. Resnick , Steven R. Volk
发明人： Jeffry J. Sniegowski , Thomas W. Krygowski , Seethambal S. Mani , Scott D. Habermehl , Dale L. Hetherington , James E. Stevens , Paul J. Resnick , Steven R. Volk
IPC分类号： H01L2100
CPC分类号： B81C1/00666 , B81C2201/0167
摘要： A process is disclosed for forming a microelectromechanical (MEM) structure on a substrate having from 5 to 6 or more layers of deposited and patterned polysilicon. The process is based on determining a radius of curvature of the substrate which is bowed due to accumulated stress in the layers of polysilicon and a sacrificial material used to buildup the MEM structure, and then providing one or more stress-compensation layers on a backside of the substrate to flatten the substrate and allow further processing.
摘要翻译：公开了一种用于在具有5至6层或更多层沉积和图案化多晶硅的衬底上形成微机电（MEM）结构的方法。该过程基于确定由于多晶硅层中的累积应力而被弯曲的衬底的曲率半径以及用于构建MEM结构的牺牲材料，然后在背面设置一个或多个应力补偿层使基板平坦化并允许进一步处理。

4. 发明授权

US06290859B1 Tungsten coating for improved wear resistance and reliability of microelectromechanical devices 有权
标题翻译：钨涂层，用于改善微机电装置的耐磨性和可靠性
公开(公告)号：US06290859B1
公开(公告)日：2001-09-18
申请号：US09439103
申请日：1999-11-12
申请人： James G. Fleming , Seethambal S. Mani , Jeffry J. Sniegowski , Robert S. Blewer
发明人： James G. Fleming , Seethambal S. Mani , Jeffry J. Sniegowski , Robert S. Blewer
IPC分类号： H01L2100
CPC分类号： B81C1/0096 , B81B3/0005 , B81B2201/035 , B81C1/00674 , B81C2201/0176 , B81C2201/112 , H01H2001/0057
摘要： A process is disclosed whereby a 5-50-nanometer-thick conformal tungsten coating can be formed over exposed semiconductor surfaces (e.g. silicon, germanium or silicon carbide) within a microelectromechanical (MEM) device for improved wear resistance and reliability. The tungsten coating is formed after cleaning the semiconductor surfaces to remove any organic material and oxide film from the surface. A final in situ cleaning step is performed by heating a substrate containing the MEM device to a temperature in the range of 200-600 ° C. in the presence of gaseous nitrogen trifluoride (NF3). The tungsten coating can then be formed by a chemical reaction between the semiconductor surfaces and tungsten hexafluoride (WF6) at an elevated temperature, preferably about 450° C. The tungsten deposition process is self-limiting and covers all exposed semiconductor surfaces including surfaces in close contact. The present invention can be applied to many different types of MEM devices including microrelays, micromirrors and microengines. Additionally, the tungsten wear-resistant coating of the present invention can be used to enhance the hardness, wear resistance, electrical conductivity, optical reflectivity and chemical inertness of one or more semiconductor surfaces within a MEM device.
摘要翻译：公开了一种方法，其中可以在微机电（MEM）装置内的暴露的半导体表面（例如硅，锗或碳化硅）上形成5-50纳米厚的共形钨涂层，以改善耐磨性和可靠性。在清洁半导体表面之后形成钨涂层，以从表面除去任何有机材料和氧化物膜。通过在含有气态三氟化氮（NF 3）的存在下，将含有MEM装置的基板加热至200-600℃的温度，进行最终的原位清洗步骤。钨涂层然后可以通过半导体表面和六氟化钨（WF6）之间的化学反应在升高的温度，优选约450℃下形成。钨沉积工艺是自限制的，并且覆盖所有暴露的半导体表面，包括紧密的表面联系。本发明可以应用于许多不同类型的MEM装置，包括微型雷达，微镜和微型引擎。此外，本发明的钨耐磨涂层可用于提高MEM装置内的一个或多个半导体表面的硬度，耐磨性，导电性，光反射率和化学惰性。

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