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    • 1. 发明申请
    • LATCH MODULE AND FREQUENCY DIVIDER
    • 锁模块和频率分路器
    • WO2009115865A1
    • 2009-09-24
    • PCT/IB2008/051059
    • 2008-03-20
    • FREESCALE SEMICONDUCTOR, INC.SAVERIO, Trotta
    • SAVERIO, Trotta
    • H03K3/00H03K21/00
    • H03K3/3562
    • A latch module comprising a sense pair of transistor elements (T 1 , T 2 ) coupled together for sensing a differential input signal at input terminals (D, Dn), a level-shift module (T 5 , T 6 ) for producing a differential output signal at output terminals (Q, Qn), and a regenerative pair of transistor elements (T 3 , T 4 ) coupled together and with the input pair (T 1 , T 2 ) for holding the output signal through the level-shift module (T 5 , T 6 ). The latch module also includes a pair of gate transistor elements (T 7 , T 8 ) connected in series respectively with the sense pair of transistor elements (T 1 , T 2 ) and with the regenerative pair of transistor elements (T 3 , T 4 ) and responsive to an alternating differential gate signal (CIk, Clk_n) to activate alternately the sense pair during sense periods and the regenerative pair during store periods. A current injector (602) provides asymmetric operation by injecting current (Itune) between at least one of the gate transistors (T 7 , T 8 ) and the corresponding sense (T 1 , T 2 ) or regenerative pair (T 3 , T 4 ) of transistor elements so that the sense periods are of different duration from the store periods. In one embodiment, the current injector (602) injects the current (Itune) to the sense pair of transistor elements (T 1 , T 2 ) in parallel with the corresponding gate transistor element (T 7 ) so that the sense periods are of greater duration than the store periods. The invention also provides a frequency divider comprising a pair of such latch modules cross-coupled in master-slave configuration.
    • 一种锁存模块,包括耦合在一起的感测对晶体管元件(T1,T2),用于感测输入端(D,Dn)上的差分输入信号,电平移位模块(T5,T6),用于产生输出端的差分输出信号 端子(Q,Qn)以及耦合在一起的输出对(T1,T2)的晶体管元件(T3,T4)的再生对,用于通过电平移位模块(T5,T6)保持输出信号。 锁存模块还包括一对栅极晶体管元件(T7,T8),分别与晶体管元件(T1,T2)的感测对和晶体管元件(T3,T4)的再生对串联并且响应于交替 差分门信号(CIk,Clk_n)在存储周期期间在感测周期期间交替地激活感测对,并且在存储周期期间激活再生对。 电流注入器(602)通过在晶体管元件的至少一个栅极晶体管(T7,T8)和对应的感测(T1,T2)或再生对(T3,T4)之间注入电流(Itune)来提供不对称的操作,使得 感测周期与存储周期的持续时间不同。 在一个实施例中,电流注入器(602)将电流(Itune)与对应的栅极晶体管元件(T7)并联地注入到晶体管元件(T1,T2)的感测对,使得感测周期比 商店期间 本发明还提供了一种分频器,包括一对在主从配置中交叉耦合的这种闩锁模块。
    • 2. 发明申请
    • MIXER CIRCUIT
    • 混频器电路
    • WO2009104055A1
    • 2009-08-27
    • PCT/IB2008/050579
    • 2008-02-18
    • FREESCALE SEMICONDUCTOR, INC.SAVERIO, Trotta
    • SAVERIO, Trotta
    • H03D7/14
    • H03D7/1425H03D7/1433H03D7/1441H03D7/1458H03D7/1491H03D2200/0033H03D2200/0043
    • A double balanced mixer circuit comprising a differential pair (102) of first amplifier elements (T 1 , T 2 ) responsive to an RF differe ntial input signal, double differential pairs (104, 106) of second amplifier elements (T 3 , T 4 , T 5 , T 6 ) responsive to an LO differential input signal, and differential output terminals (406) connected with the second amplifier paths. Coup ling elements provide first and second parallel DC connections between DC voltage supply rails (+V, -V) for the first and the double second amplifier paths respecti vely and a series RF connection of the first and second amplifier paths between the supply rails so as to produce a mixed differential amplified signal at the differ ential output terminals (406). The coupling elements include respective transmission lines (Z L6 , Z L13 & Z L7 , Z L14 ) in the first amplifier paths connected bet ween one of the DC voltage supply rails (+V) and respective ones of the first amplifier elements (T 1 , T 2 ) and a common transmission line (Z L1) connected between the other of the DC voltage supply rails (-V) and both the first amplifier elements (T 1 , T 2 ).
    • 一种双平衡混频器电路,包括响应于RF差分输入信号的第一放大器元件(T1,T2)的差分对(102),第二放大器元件(T3,T4,T5,T6)的双差分对(104,106) )和与第二放大器路径连接的差分输出端(406)。 耦合元件在第一和第二放大器路径之间提供直流电源电压轨(+ V,-V)之间的第一和第二并联直流连接,以及电源轨之间的第一和第二放大器路径的串联RF连接, 以在不同的输出端(406)产生混合的差分放大信号。 耦合元件包括在直流电源电压轨(+ V)中的一个和第一放大器元件(T1,T2)中的一个连接的第一放大器路径中的相应的传输线(ZL6,ZL13和ZL7,ZL14) 公共传输线(Z L1)连接在另一个直流电压电源轨(-V)和两个第一放大器元件(T1,T2)之间。
    • 3. 发明授权
    • Phased-array receiver, radar system and vehicle
    • 相控阵接收机,雷达系统和车辆
    • US09411039B2
    • 2016-08-09
    • US13977087
    • 2011-01-21
    • Bernhard DehlinkSaverio Trotta
    • Bernhard DehlinkSaverio Trotta
    • G01S7/03G01S3/04G01S13/93G01S13/34G01S7/288G01S7/35H01Q3/26H01Q1/32
    • G01S7/03G01S3/043G01S7/032G01S13/931G01S2007/2886G01S2007/358H01Q1/3233H01Q3/26
    • A phased-array receiver comprises a plurality of analog beamforming receive channels, each comprising an antenna element arranged to receive a radio frequency signal and a channel output arranged to provide an analog channel output signal. At least one of the plurality of analog beamforming receive channels comprises an in-phase downconversion mixing circuit connected to the antenna element and a local oscillator source and arranged to provide a downconverted in-phase signal to a phase rotation circuit, and a quadrature downconversion mixing circuit connected to the antenna element and the local oscillator source and arranged to provide a downconverted quadrature signal to the phase rotation circuit. The phase rotation circuit is arranged to provide to the channel output a phase-shifted analog output signal generated from the downconverted in-phase signal and the downconverted quadrature signal.
    • 相控阵接收机包括多个模拟波束成形接收信道,每个接收信道包括布置成接收射频信号的天线元件和布置成提供模拟信道输出信号的信道输出。 多个模拟波束成形接收通道中的至少一个包括连接到天线元件的同相下变频混合电路和本地振荡器源,并且被布置成向相位旋转电路提供下变频的同相信号,并且正交下变频混频 连接到天线元件和本地振荡器源并且被布置成向相位旋转电路提供下变频的正交信号。 相位旋转电路被布置成向通道输出提供从下变频同相信号和下变频正交信号产生的相移模拟输出信号。
    • 6. 发明申请
    • PUSH-PUSH OSCILLATOR CIRCUIT
    • 推压振荡器电路
    • US20130141175A1
    • 2013-06-06
    • US13814764
    • 2010-08-26
    • Yi YinHao LiSaverio Trotta
    • Yi YinHao LiSaverio Trotta
    • H02M7/5383
    • H02M7/53835H03B5/1209H03B5/1218H03B5/1231H03B5/124H03B5/1847H03B25/00H03B2200/007
    • A push-push oscillator circuit with a first oscillation branch with a first active device and a first tank adapted to provide a signal having a fundamental frequency f0, a second oscillation branch with a second active device and a second tank symmetrical to the first oscillation branch and adapted to provide a signal having the fundamental frequency f0. Output branches are coupled to the first oscillation branch and the second oscillation branch to provide signals having the second harmonic frequency 2f0 of the fundamental signal based on the signals having the fundamental frequency f0 and/or to provide signals having the fundamental frequency f0; The push-push oscillator circuit further comprises at least one terminal branch with a terminal adapted to provide a component of a differential signal having the second harmonic frequency 2f0 or the fundamental frequency f0. The at least one terminal branch comprises a RF stub.
    • 一种具有第一振荡分支的推挽振荡器电路,具有第一有源器件和适于提供具有基频f0的信号的第一振荡器,具有第二有源器件的第二振荡分支和与第一振荡分支对称的第二振荡器 并且适于提供具有基频f0的信号。 输出分支耦合到第一振荡分支和第二振荡分支,以基于具有基频f0的信号和/或提供具有基频f0的信号来提供具有基波信号的二次谐波频率2f0的信号; 推挽振荡器电路还包括至少一个终端分支,其具有适于提供具有二次谐波频率2f0或基频f0的差分信号的分量的终端。 至少一个终端分支包括RF短截线。
    • 8. 发明授权
    • Latch circuit, flip-flop circuit and frequency divider
    • 锁存电路,触发器电路和分频器
    • US08797078B2
    • 2014-08-05
    • US13811921
    • 2010-07-27
    • Saverio Trotta
    • Saverio Trotta
    • H03K3/286
    • H03K3/00H03B19/14H03K3/011H03K3/2885
    • The invention pertains to a latch circuit comprising a sensing arrangement with one or more sensing transistors adapted to sense an input signal and to provide a first signal based on the sensed input signal, and a sensing arrangement switch device connected or connectable to a first current source, the sensing arrangement switch device being adapted to switch on or off a current to the one or more sensing transistors based on a first clock signal. The latch circuit further comprises a storage arrangement with one or more storage transistors adapted to store the first signal and to provide a second signal based on the first signal, and a storage arrangement switching device connected or connectable to the first current source or a second current source, the storage arrangement switching device being adapted to switch on or off a current to the storage transistors based on a second clock signal, as well as a tuning arrangement connected or connectable to a temperature sensor, the tuning arrangement being adapted to bias a current of the sensing arrangement and/or the storage arrangement based on a temperature signal provided by the temperature sensor. The invention also pertains to a flip-flop circuit with two or more latch circuits and a frequency divider comprising at least one latch circuit as described.
    • 本发明涉及一种锁存电路,其包括具有一个或多个感测晶体管的感测装置,其适于感测输入信号并且基于感测到的输入信号提供第一信号,以及感测布置开关装置,其连接或连接到第一电流源 感测装置开关装置适于基于第一时钟信号将电流接通或断开到一个或多个感测晶体管。 锁存电路还包括具有适于存储第一信号的一个或多个存储晶体管并基于第一信号提供第二信号的存储装置,以及连接或可连接到第一电流源的存储装置开关装置或第二电流 源,存储布置开关装置适于基于第二时钟信号将电流接通或断开到存储晶体管,以及连接或可连接到温度传感器的调谐装置,所述调谐装置适于偏置电流 基于由温度传感器提供的温度信号的感测装置和/或存储装置。 本发明还涉及具有两个或更多个锁存电路的触发器电路和包括如上所述的至少一个锁存电路的分频器。
    • 9. 发明授权
    • Electrical circuit having a controllable oscillator
    • 具有可控振荡器的电路
    • US08598926B2
    • 2013-12-03
    • US13370973
    • 2012-02-10
    • Saverio Trotta
    • Saverio Trotta
    • H03L7/06
    • H03L7/06H03L2207/12
    • An electrical circuit including a controllable oscillator, a transmission line and a control loop. The controllable oscillator is configured to generate an oscillating signal. The transmission line is connected to an output of the oscillator, wherein the transmission line has a length which is a fraction of a wavelength of the oscillating signal. The control loop is configured to detect a difference between a first value of a signal parameter of the oscillating signal and a second value of the signal parameter of the oscillating signal having passed the transmission line. Furthermore, the control loop is configured to control the controllable oscillator in accordance with the difference.
    • 包括可控振荡器,传输线和控制回路的电路。 可控振荡器被配置为产生振荡信号。 传输线连接到振荡器的输出,其中传输线的长度是振荡信号波长的一部分。 控制回路被配置为检测振荡信号的信号参数的第一值与经过传输线的振荡信号的信号参数的第二值之间的差值。 此外,控制环路被配置为根据差异来控制可控振荡器。