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1. 发明申请

US20130181349A1 SEMICONDUCTOR DEVICE HAVING THROUGH-SUBSTRATE VIA 审中-公开
标题翻译：具有通过基底的半导体器件
公开(公告)号：US20130181349A1
公开(公告)日：2013-07-18
申请号：US13599041
申请日：2012-08-30
申请人： Chie KOYAMA , Satoyuki Miyako , Eiji Sato
发明人： Chie KOYAMA , Satoyuki Miyako , Eiji Sato
IPC分类号： H01L23/498
CPC分类号： H01L23/481 , H01L21/76224 , H01L23/5225 , H01L23/5286 , H01L27/14618 , H01L27/14636 , H01L2924/0002 , H01L2924/00
摘要： According to an embodiment, a semiconductor device includes a first circuit block, a first through-substrate via, and a back surface wiring. The first circuit block is provided on a surface side of a semiconductor substrate. The first through-substrate via is provided along a circumference of the first circuit block so as to separate the first circuit block from other circuit blocks. The first circuit block is provided so as to penetrate the surface of the semiconductor substrate. The first circuit block is isolated from the surroundings. The first circuit block has conductivity. The back surface wiring is provided on the back surface side of the semiconductor substrate. The back surface wiring is connected to the first through-substrate via. The back surface wiring connects the first through-substrate via to a power supply terminal or a shield potential terminal.
摘要翻译：根据实施例，半导体器件包括第一电路块，第一贯穿衬底通孔和背面布线。第一电路块设置在半导体衬底的表面侧。沿着第一电路块的圆周设置第一贯穿衬底通孔，以将第一电路块与其它电路块分离。第一电路块被设置为穿透半导体衬底的表面。第一个电路块与周围环境隔绝。第一个电路块具有导电性。背面布线设置在半导体基板的背面侧。背面布线连接到第一贯穿基板通孔。背面布线将第一贯穿基板通孔连接到电源端子或屏蔽电位端子。

2. 发明申请

US20080298155A1 SEMICONDUCTOR MEMORY DEVICE COMPENSATING LEAKAGE CURRENT 失效
标题翻译：半导体存储器件补偿泄漏电流
公开(公告)号：US20080298155A1
公开(公告)日：2008-12-04
申请号：US12124799
申请日：2008-05-21
申请人： Satoyuki Miyako
发明人： Satoyuki Miyako
IPC分类号： G11C5/14
CPC分类号： G11C11/413 , G11C7/12 , G11C17/00
摘要： A cell array has a plurality of memory cells arranged in a matrix. Each one terminal of a plurality of switching circuits is connected to a bit line. A leakage current compensating circuit has an output node connected in common to the other terminal of the switching circuit. The leakage current compensating circuit comprises a plurality of MOSFETs. Each MOSFET has the same conduction type as a MOSFET whose output node is directly connected to the bit line in the memory cell. Each MOSFET of the leakage current compensating circuit has a gate electrode connected to a first voltage node and a source electrode connected to a second voltage node, and thereby, being biased so that the MOSFET turns off.
摘要翻译：单元阵列具有以矩阵形式布置的多个存储单元。多个开关电路的每个端子连接到位线。泄漏电流补偿电路具有与开关电路的另一端共同连接的输出节点。漏电流补偿电路包括多个MOSFET。每个MOSFET具有与其输出节点直接连接到存储器单元中的位线的MOSFET相同的导通类型。泄漏电流补偿电路的每个MOSFET具有连接到第一电压节点的栅电极和连接到第二电压节点的源电极，从而被偏置以使MOSFET关断。

3. 发明授权

US07848171B2 Semiconductor memory device compensating leakage current 失效
标题翻译：半导体存储器件补偿漏电流
公开(公告)号：US07848171B2
公开(公告)日：2010-12-07
申请号：US12124799
申请日：2008-05-21
申请人： Satoyuki Miyako
发明人： Satoyuki Miyako
IPC分类号： G11C5/14
CPC分类号： G11C11/413 , G11C7/12 , G11C17/00
摘要： A cell array has a plurality of memory cells arranged in a matrix. Each one terminal of a plurality of switching circuits is connected to a bit line. A leakage current compensating circuit has an output node connected in common to the other terminal of the switching circuit. The leakage current compensating circuit comprises a plurality of MOSFETs. Each MOSFET has the same conduction type as a MOSFET whose output node is directly connected to the bit line in the memory cell. Each MOSFET of the leakage current compensating circuit has a gate electrode connected to a first voltage node and a source electrode connected to a second voltage node, and thereby, being biased so that the MOSFET turns off.
摘要翻译：单元阵列具有以矩阵形式布置的多个存储单元。多个开关电路的每个端子连接到位线。泄漏电流补偿电路具有与开关电路的另一端共同连接的输出节点。漏电流补偿电路包括多个MOSFET。每个MOSFET具有与其输出节点直接连接到存储器单元中的位线的MOSFET相同的导通类型。泄漏电流补偿电路的每个MOSFET具有连接到第一电压节点的栅电极和连接到第二电压节点的源电极，从而被偏置以使MOSFET关断。

4. 发明授权

US06486565B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06486565B2
公开(公告)日：2002-11-26
申请号：US09818432
申请日：2001-03-26
申请人： Satoyuki Miyako
发明人： Satoyuki Miyako
IPC分类号： H01L23544
CPC分类号： H01L22/34 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： The dimension measurement and management of a mask or a wafer are facilitated by using a dummy pattern having a configuration and arrangement capable of achieving a plurality of objects. In the entire region or a major region of an optional wiring layer on a semiconductor chip and in the space between the adjacent patterns in an actual pattern portion, dummy patterns for controlling the coverage and density of a pattern in the wiring layer are regularly arranged. All or some of the dummy patterns are dummy patterns for the dimension measurement including the main size (width and distance) required for the dimension management of the wiring layer.
摘要翻译：通过使用具有能够实现多个物体的配置和布置的虚拟图案，便于掩模或晶片的尺寸测量和管理。在实际图案部分的整个区域或半导体芯片上的可选配线层的主要区域和相邻图案之间的空间中，规则地布置用于控制布线层中的图案的覆盖和密度的虚拟图案。所有或一些虚拟图案是用于尺寸测量的虚拟图案，包括布线层的尺寸管理所需的主要尺寸（宽度和距离）。

5. 发明申请

US20070064465A1 ROM storing information by using pair of memory cells 失效
公开(公告)号：US20070064465A1
公开(公告)日：2007-03-22
申请号：US11519232
申请日：2006-09-12
申请人： Satoyuki Miyako
发明人： Satoyuki Miyako
IPC分类号： G11C17/00
CPC分类号： G11C17/12
摘要： Disclosed is a semiconductor device including a memory cell array, word lines, bit lines, and a signal difference determination circuit. In the memory cell array, memory cells each formed by connecting a MOS transistor and resistor in series are arranged in a matrix. The word lines are connected to the gates of the MOS transistors of the memory cells in the same row of the memory cell array. The bit lines are provided so as to correspond to the columns of the memory cell array. Each bit line is connected to one terminal of a corresponding one of the resistors of the memory cells in the same column. The signal difference determination circuit compares two output signals read to two bit lines from a pair of memory cells, thereby determining stored information in the pair of memory cells.

6. 发明授权

US07310263B2 ROM storing information by using pair of memory cells 失效
标题翻译： ROM通过使用一对存储单元存储信息
公开(公告)号：US07310263B2
公开(公告)日：2007-12-18
申请号：US11519232
申请日：2006-09-12
申请人： Satoyuki Miyako
发明人： Satoyuki Miyako
IPC分类号： G11C11/00
CPC分类号： G11C17/12
摘要： Disclosed is a semiconductor device including a memory cell array, word lines, bit lines, and a signal difference determination circuit. In the memory cell array, memory cells each formed by connecting a MOS transistor and resistor in series are arranged in a matrix. The word lines are connected to the gates of the MOS transistors of the memory cells in the same row of the memory cell array. The bit lines are provided so as to correspond to the columns of the memory cell array. Each bit line is connected to one terminal of a corresponding one of the resistors of the memory cells in the same column. The signal difference determination circuit compares two output signals read to two bit lines from a pair of memory cells, thereby determining stored information in the pair of memory cells.
摘要翻译：公开了一种包括存储单元阵列，字线，位线和信号差分确定电路的半导体器件。在存储单元阵列中，通过串联连接MOS晶体管和电阻器而形成的存储单元被布置成矩阵。字线连接到存储单元阵列的同一行中的存储单元的MOS晶体管的栅极。位线被提供以对应于存储单元阵列的列。每个位线连接到同一列中的存储器单元的相应电阻器的一个端子。信号差分确定电路将从一对存储单元读取的两个位线的两个输出信号进行比较，从而确定存储单元对中存储的信息。

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