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1. 发明专利

JP2017088158A 車両用マルチソケット审中-公开
公开(公告)号：JP2017088158A
公开(公告)日：2017-05-25
申请号：JP2016159704
申请日：2016-08-16
申请人：星光産業株式会社 , Seiko Sangyo Kk , リーサンドンLee Sang Don , Sang Don Lee , リーサンドンLee Sang Don
发明人： LEE SANG DON
IPC分类号： B60R16/04 , B60N3/14 , H02G3/08
摘要：【課題】ソケット本体をコンパクトに製作できる車両用マルチソケットを提供する。【解決手段】本発明の一実施形態に係る車両用マルチソケットは、電子装置のジャックが挿入される複数のソケット溝が形成されたソケットハウジングと、ソケットハウジングの内部に装着される接続端子部と、接続端子部にケーブルによって連結され、車両の電源供給用ソケットに挿入されて接続されるプラグと、を含んでいる。ソケットハウジングは、上部が開放されたボックス形状を有し、さらに、前面には、上端の一部区間が開放されている形状を有するソケット溝が形成されている下部ケースと、下部ケースの開放されている上面を覆い、さらに、ソケット溝の開放されている一部区間に対応する部分が開放されている第1切開部を有する上部ケースと、上部ケースと下部ケースとの間で挟持され、第1切開部を弾性的にカバーするソフト蓋と、を含む。【選択図】図1

2. 发明专利

AU3366089A LOCKING NEEDLE ASSEMBLY IN A HYPODERMIC SYRINGE 未知
公开(公告)号：AU3366089A
公开(公告)日：1989-10-16
申请号：AU3366089
申请日：1989-03-24
申请人： SANG DON LEE
发明人： LEE SANG DON
IPC分类号： A61M5/34 , A61M5/50 , A61M5/00

3. 发明授权

US08198167B2 Method of manufacuturing semiconductor memory apparatus and semiconductor memory apparatus manufactured thereby 有权
标题翻译：制造半导体存储装置的半导体存储装置及其制造方法
公开(公告)号：US08198167B2
公开(公告)日：2012-06-12
申请号：US12254729
申请日：2008-10-20
申请人： Sang Don Lee
发明人： Sang Don Lee
IPC分类号： H01L21/20
CPC分类号： H01L27/10885 , H01L27/0207 , H01L27/10855 , H01L27/10888
摘要： A method of manufacturing a semiconductor memory apparatus includes fabricating a cell array to reduce parasite capacitance generated between a bit line and a gate pattern. The method may include determining a plug region by a storage-node plug contact mask and a bit line plug mask. The method may further include: forming a gate pattern of a cell transistor and depositing an insulation layer over a structure including the gate pattern; and forming a hard mask layer over the insulation layer.
摘要翻译：制造半导体存储装置的方法包括制造单元阵列以减少在位线和栅极图案之间产生的寄生电容。该方法可以包括通过存储节点插头接触掩码和位线插头掩码来确定插头区域。该方法还可以包括：形成单元晶体管的栅极图案，并在包括栅极图案的结构之上沉积绝缘层; 以及在所述绝缘层上形成硬掩模层。

4. 发明授权

US08110871B2 Semiconductor device with recess and fin structure 有权
标题翻译：具有凹槽和鳍结构的半导体器件
公开(公告)号：US08110871B2
公开(公告)日：2012-02-07
申请号：US12323391
申请日：2008-11-25
申请人： Sang Don Lee , Sung Woong Chung
发明人： Sang Don Lee , Sung Woong Chung
IPC分类号： H01L29/78
CPC分类号： H01L29/66795 , H01L21/823437 , H01L29/4236 , H01L29/66621 , H01L29/7851
摘要： The semiconductor device includes an active region, a recess, a Fin channel region, a gate insulating film, and a gate electrode. The active region is defined by a device isolation structure formed in a semiconductor substrate. The recess is formed by etching the active region and its neighboring device isolation structure using an island shaped recess gate mask as an etching mask. The Fin channel region is formed on the semiconductor substrate at a lower part of the recess. The gate insulating film is formed over the active region including the Fin channel region and the recess. The gate electrode is formed over the gate insulating film to fill up the Fin channel region and the recess.
摘要翻译：半导体器件包括有源区，凹槽，Fin沟道区，栅极绝缘膜和栅电极。有源区由半导体衬底中形成的器件隔离结构限定。通过使用岛状凹陷栅极掩模作为蚀刻掩模来蚀刻有源区及其邻近的器件隔离结构来形成凹部。鳍状沟道区在凹部的下部形成在半导体衬底上。栅极绝缘膜形成在包括鳍状沟道区域和凹部的有源区域上。栅电极形成在栅极绝缘膜上，以填充鳍沟道区域和凹槽。

5. 发明授权

US07785969B2 Method for forming semiconductor device 失效
公开(公告)号：US07785969B2
公开(公告)日：2010-08-31
申请号：US12755222
申请日：2010-04-06
申请人： Sang Don Lee
发明人： Sang Don Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/7851 , H01L29/66795 , H01L29/66818
摘要： A method for forming a semiconductor device of the present invention solves problems in a process for forming a fin type gate including a recess region, such as, a complicated process, low production margin, and difficulty in forming an accurate fin shape. In a process for forming an isolation dielectric film defining an active region, a nitride film pattern is formed in such a manner that the size of the nitride film is adjusted according to line width of a fin portion in a fin type active region formed in a subsequent process step, and an isolation dielectric film is formed in every region except for the nitride film pattern of a semiconductor substrate. Then, a recess is etched, and the isolation dielectric film is removed from a region where the line width of the nitride film pattern was reduced to a certain degree. Consequently, a process margin for forming a fin type active region is increased, and the shape of a fin shaped portion can be adjusted accurately, which together contribute to improved electrical properties in the semiconductor devices.

6. 发明申请

US20100190305A1 METHOD FOR FORMING SEMICONDUCTOR DEVICE 失效
标题翻译：形成半导体器件的方法
公开(公告)号：US20100190305A1
公开(公告)日：2010-07-29
申请号：US12755222
申请日：2010-04-06
申请人： Sang Don Lee
发明人： Sang Don Lee
IPC分类号： H01L21/8242 , H01L21/28
CPC分类号： H01L29/7851 , H01L29/66795 , H01L29/66818
摘要： A method for forming a semiconductor device of the present invention solves problems in a process for forming a fin type gate including a recess region, such as, a complicated process, low production margin, and difficulty in forming an accurate fin shape. In a process for forming an isolation dielectric film defining an active region, a nitride film pattern is formed in such a manner that the size of the nitride film is adjusted according to line width of a fin portion in a fin type active region formed in a subsequent process step, and an isolation dielectric film is formed in every region except for the nitride film pattern of a semiconductor substrate. Then, a recess is etched, and the isolation dielectric film is removed from a region where the line width of the nitride film pattern was reduced to a certain degree. Consequently, a process margin for forming a fin type active region is increased, and the shape of a fin shaped portion can be adjusted accurately, which together contribute to improved electrical properties in the semiconductor devices.
摘要翻译：本发明的半导体装置的形成方法解决了形成包括凹陷区域的翅片型浇口的工艺，复杂的工艺，低的生产裕度以及难以形成精确的翅片形状的问题。在形成限定有源区的隔离电介质膜的工艺中，以如下方式形成氮化膜图案：使氮化膜的尺寸根据在随后的工艺步骤，并且除了半导体衬底的氮化物膜图案之外的每个区域中形成隔离电介质膜。然后，蚀刻凹部，从氮化膜图案的线宽减小到一定程度的区域去除隔离电介质膜。因此，用于形成翅片型有源区的工艺余量增加，并且可以精确地调节翅片形状部分的形状，这一起有助于改善半导体器件中的电性能。

7. 发明授权

US07692251B2 Transistor for semiconductor device and method of forming the same 失效
标题翻译：用于半导体器件的晶体管及其形成方法
公开(公告)号：US07692251B2
公开(公告)日：2010-04-06
申请号：US11284957
申请日：2005-11-23
申请人： Sung Woong Chung , Sang Don Lee
发明人： Sung Woong Chung , Sang Don Lee
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L21/823437 , H01L21/823412 , H01L21/823481 , H01L29/66818 , H01L29/7851 , H01L29/7853 , Y10S257/903
摘要： Disclosed herein is a transistor for a semiconductor device and a method of forming the same. According to the present invention, a novel transistor structure combining a plane channel transistor and a fin-type channel transistor formed on the semiconductor substrate is provided to secure a sufficient channel width as compared to that of the plane channel transistor, thereby satisfying drive current regulated for the transistor.
摘要翻译：本文公开了一种用于半导体器件的晶体管及其形成方法。根据本发明，提供组合平面沟道晶体管和形成在半导体衬底上的鳍型沟道晶体管的新型晶体管结构，以确保与平面沟道晶体管相比足够的沟道宽度，由此满足驱动电流调节用于晶体管。

8. 发明授权

US07675112B2 Semiconductor device with a surrounded channel transistor 失效
标题翻译：具有四通道晶体管的半导体器件
公开(公告)号：US07675112B2
公开(公告)日：2010-03-09
申请号：US11585106
申请日：2006-10-24
申请人： Sang Don Lee
发明人： Sang Don Lee
IPC分类号： H01L29/94
CPC分类号： H01L29/66621 , H01L27/10876 , H01L27/10879 , H01L29/42336 , H01L29/4236 , H01L29/42392 , H01L29/66795 , H01L29/7834 , H01L29/785
摘要： The semiconductor device includes a device isolation structure, a surrounded channel structure, and a gate electrode. The device isolation structure is formed in a semiconductor substrate to define an active region. The surrounded channel structure connecting source/drain regions is separated from the semiconductor substrate under the active region by a given distance. The gate electrode surrounds the surrounded channel structure.
摘要翻译：半导体器件包括器件隔离结构，包围的通道结构和栅电极。器件隔离结构形成在半导体衬底中以限定有源区。连接源极/漏极区域的被包围的沟道结构在有源区域之下与半导体衬底分离给定的距离。栅电极围绕着包围的通道结构。

9. 发明申请

US20100048008A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20100048008A1
公开(公告)日：2010-02-25
申请号：US12605971
申请日：2009-10-26
申请人： Sang Don LEE
发明人： Sang Don LEE
IPC分类号： H01L21/28 , H01L21/311
CPC分类号： H01L21/823437 , H01L27/10876 , H01L29/66621 , H01L29/7834
摘要： A method for manufacturing a semiconductor device includes forming a recess with a device separating film and a first hard mask layer so that a pad nitride film for defining a recess gate region may remain with a conventional mask. The method additionally the recess gate region to facilitate a subsequent process for etching a gate electrode without a step difference between the device separating film.
摘要翻译：一种制造半导体器件的方法包括：通过器件分离膜和第一硬掩模层形成凹槽，从而用常规掩模保留用于限定凹陷栅区的衬垫氮化物膜。该方法另外还包括凹槽栅极区域，以便于在器件分离膜之间没有阶差的情况下进行蚀刻栅电极的后续处理。

10. 发明申请

US20100022057A1 METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING A FIN CHANNEL TRANSISTOR 审中-公开
标题翻译：用于形成具有FIN通道晶体管的半导体器件的方法
公开(公告)号：US20100022057A1
公开(公告)日：2010-01-28
申请号：US12569802
申请日：2009-09-29
申请人： Sung Woong Chung , Sang Don Lee
发明人： Sung Woong Chung , Sang Don Lee
IPC分类号： H01L21/762 , H01L21/8242 , H01L21/28
CPC分类号： H01L29/7851 , H01L27/10826 , H01L27/10873 , H01L27/10879 , H01L29/0653 , H01L29/66795
摘要： The semiconductor device includes a device isolation structure formed in a semiconductor substrate to define an active region having a recess region at a lower part of sidewalls thereof. The semiconductor device additionally has a fin channel region protruded over the device isolation structure in a longitudinal direction of a gate region; a gate insulating film formed over the semiconductor substrate including the protruded fin channel region; and a gate electrode formed over the gate insulating film to fill up the protruded fin channel region.
摘要翻译：半导体器件包括形成在半导体衬底中的器件隔离结构，以限定在其侧壁的下部具有凹陷区域的有源区。半导体器件还具有在栅极区域的纵向方向上在器件隔离结构上突出的鳍状沟道区域; 形成在所述半导体衬底上的栅极绝缘膜，所述栅极绝缘膜包括所述突出的鳍状沟道区域; 以及形成在所述栅极绝缘膜上方以填充所述突出的鳍状沟道区域的栅电极。

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