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1. 发明授权

US09183910B2 Semiconductor memory devices for alternately selecting bit lines 有权
标题翻译：用于交替选择位线的半导体存储器件
公开(公告)号：US09183910B2
公开(公告)日：2015-11-10
申请号：US13907223
申请日：2013-05-31
申请人： Yun-Sang Lee , Dong-Seok Kang , Sang-Beom Kang , Chan-Kyung Kim , Chul-Woo Park , Dong-Hyun Sohn , Hyung-Rok Oh
发明人： Yun-Sang Lee , Dong-Seok Kang , Sang-Beom Kang , Chan-Kyung Kim , Chul-Woo Park , Dong-Hyun Sohn , Hyung-Rok Oh
IPC分类号： G11C11/16 , G11C7/12
CPC分类号： G11C11/1653 , G11C7/12 , G11C11/16 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C11/1697
摘要： A semiconductor memory device includes a cell array including one or more bank groups, where each of the one or more bank groups includes a plurality of banks and each of the plurality of banks includes a plurality of spin transfer torque magneto resistive random access memory (STT-MRAM) cells. The semiconductor memory device further includes a source voltage generating unit for applying a voltage to a source line connected to the each of the plurality of STT-MRAM cells, and a command decoder for decoding a command from an external source in order to perform read and write operations on the plurality of STT-MRAM cells. The command includes a combination of at least one signal of a row address strobe (RAS), a column address strobe (CAS), a chip selecting signal (CS), a write enable signal (WE), and a clock enable signal (CKE).
摘要翻译：半导体存储器件包括一个单元阵列，其包括一个或多个存储体组，其中一个或多个存储体组中的每个组包括多个存储体，并且多个存储体中的每一个存储体包括多个自旋传递转矩磁阻随机存取存储器（STT -MRAM）细胞。半导体存储器件还包括用于向连接到多个STT-MRAM单元中的每一个的源极线施加电压的源极电压产生单元，以及用于对来自外部源的命令进行解码的命令解码器，以执行读取和对多个STT-MRAM单元进行写入操作。该命令包括行地址选通（RAS），列地址选通（CAS），片选信号（CS），写使能信号（WE）和时钟使能信号（CKE）的至少一个信号）。

2. 发明授权

US08780656B2 Stacked memory device and method of repairing same 失效
标题翻译：堆叠式存储器件及其修复方法
公开(公告)号：US08780656B2
公开(公告)日：2014-07-15
申请号：US13015847
申请日：2011-01-28
申请人： Chul-Woo Park , Hong-Sun Hwang , Sang-Beom Kang , Won-Seok Lee
发明人： Chul-Woo Park , Hong-Sun Hwang , Sang-Beom Kang , Won-Seok Lee
IPC分类号： G11C7/00 , G11C5/02
CPC分类号： G11C5/025 , G11C29/80
摘要： A stacked semiconductor memory device comprises memory cell array layers that are stacked in an inverted wedge shape and have different redundancy sizes from each other. The stacked semiconductor memory device has space for vertical connection between layers, a relatively small size, and a relatively high yield.
摘要翻译：层叠的半导体存储器件包括以倒置的楔形堆叠并且具有彼此不同的冗余尺寸的存储单元阵列层。层叠的半导体存储器件具有用于层之间的垂直连接的空间，相对较小的尺寸和相对较高的产量。

3. 发明授权

US08136017B2 Multi-layer semiconductor memory device comprising error checking and correction (ECC) engine and related ECC method 有权
标题翻译：多层半导体存储器件包括纠错（ECC）引擎和相关的ECC方法
公开(公告)号：US08136017B2
公开(公告)日：2012-03-13
申请号：US12036414
申请日：2008-02-25
申请人： Hyung-rok Oh , Sang-beom Kang , Woo-yeong Cho , Joon-min Park
发明人： Hyung-rok Oh , Sang-beom Kang , Woo-yeong Cho , Joon-min Park
IPC分类号： G11C29/00
CPC分类号： G06F11/1008 , G11C5/02
摘要： Embodiments of the invention provide a multi-layer semiconductor memory device and a related error checking and correction (ECC) method. The multi-layer semiconductor memory device includes first and second memory cell array layers, wherein the first memory cell array layer stores first payload data. The multi-layer semiconductor memory device also includes an ECC engine selectively connected to the second memory cell array layer and configured to receive the first payload data, generate first parity data corresponding to the first payload data, and store the first parity data exclusively in the second memory cell array layer.
摘要翻译：本发明的实施例提供一种多层半导体存储器件和相关的错误校正和校正（ECC）方法。多层半导体存储器件包括第一和第二存储单元阵列层，其中第一存储单元阵列层存储第一有效载荷数据。多层半导体存储器件还包括选择性地连接到第二存储单元阵列层并被配置为接收第一有效载荷数据的ECC引擎，生成与第一有效载荷数据相对应的第一奇偶校验数据，并将第一奇偶校验数据专门存储在第二存储单元阵列层。

4. 发明申请

US20110103134A1 RESISTANCE RANDOM ACCESS MEMORY HAVING COMMON SOURCE LINE 审中-公开
标题翻译：具有普通源线的电阻随机存取存储器
公开(公告)号：US20110103134A1
公开(公告)日：2011-05-05
申请号：US13004251
申请日：2011-01-11
申请人： Hyung-Rok OH , Sang-Beom KANG , Joon-Min PARK , Woo-Yeong CHO
发明人： Hyung-Rok OH , Sang-Beom KANG , Joon-Min PARK , Woo-Yeong CHO
IPC分类号： G11C11/40
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/0071 , G11C2013/009 , G11C2213/31 , G11C2213/79
摘要： A method writes data to a resistance random access memory (RRAM) memory cell through first and second write paths, and includes; applying a positive source voltage to a selected source line, applying a word line drive voltage to a selected word line, and applying a voltage at least twice the level of the positive source voltage to a selected bit line via the first write path when writing data having the first state in the memory cell, and applying a ground voltage to the selected bit line via the second write path when writing data having the second state in the memory cell.
摘要翻译：一种方法通过第一和第二写入路径将数据写入电阻随机存取存储器（RRAM）存储单元，并且包括：对所选择的源极线施加正的源极电压，将字线驱动电压施加到所选择的字线，并且当写入数据时，通过第一写入路径将正的源极电压的电平至少两倍的电压施加到所选择的位线在存储单元中具有第一状态，并且当在存储单元中写入具有第二状态的数据时，经由第二写入路径将接地电压施加到所选择的位线。

5. 发明授权

US07903448B2 Resistance random access memory having common source line 有权
标题翻译：具有共同源极线的电阻随机存取存储器
公开(公告)号：US07903448B2
公开(公告)日：2011-03-08
申请号：US11964142
申请日：2007-12-26
申请人： Hyung-Rok Oh , Sang-Beom Kang , Joon-Min Park , Woo-Yeong Cho
发明人： Hyung-Rok Oh , Sang-Beom Kang , Joon-Min Park , Woo-Yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/0071 , G11C2013/009 , G11C2213/31 , G11C2213/79
摘要： A resistance random access memory (RRAM) having a source line shared structure and an associated data access method. The RRAM, in which a write operation of writing data of first state and second state to a selected memory cell is performed through first and second write paths having mutually opposite directions, includes word lines, bit lines, a memory cell array and a plurality of source lines. The memory cell array includes a plurality of memory cells each constructed of an access transistor coupled to a resistive memory device. The memory cells are disposed in a matrix of rows and columns and located at each intersection of a word line and a bit line. Each of the plurality of source lines is disposed between a pair of word lines and in the same direction as the word lines. A positive voltage is applied to a source line in a memory cell write operation. Through the source line shared structure, occupied chip area is reduced and, in a write operating mode, a bit line potential can be determined within a positive voltage level range.
摘要翻译：具有源线共享结构的电阻随机存取存储器（RRAM）和相关联的数据存取方法。其中通过具有相互相反方向的第一和第二写入路径来执行将第一状态和第二状态的数据写入所选存储单元的写入操作，包括字线，位线，存储单元阵列和多个源线。存储单元阵列包括多个存储单元，每个存储单元由耦合到电阻存储器件的存取晶体管构成。存储单元被布置成行和列的矩阵并且位于字线和位线的每个交叉点处。多个源极线中的每一个被设置在一对字线之间并且在与字线相同的方向上。在存储单元写入操作中，将正电压施加到源极线。通过源极线共享结构，占用的芯片面积减小，并且在写入操作模式中，可以在正电压电平范围内确定位线电位。

6. 发明申请

US20100309705A1 Stacked memory devices 有权
标题翻译：堆叠式存储器件
公开(公告)号：US20100309705A1
公开(公告)日：2010-12-09
申请号：US12662785
申请日：2010-05-04
申请人： Seung-eon Ahn , Ho-jung Kim , Chul-woo Park , Sang-beom Kang , Hyun-ho Choi
发明人： Seung-eon Ahn , Ho-jung Kim , Chul-woo Park , Sang-beom Kang , Hyun-ho Choi
IPC分类号： G11C5/02
CPC分类号： G11C5/025 , G11C5/02 , G11C8/10 , G11C13/0004 , G11C13/0023 , G11C13/0028 , G11C2213/71 , G11C2213/72
摘要： A stacked memory device may include a substrate, a plurality of memory groups sequentially stacked on the substrate, each memory group including at least one memory layer, a plurality of X-decoder layers, at least one of the plurality of X-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups, and a plurality of Y-decoder layers disposed alternately with the plurality of X-decoder layers, at least one of the plurality of Y-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups.
摘要翻译：层叠的存储器件可以包括衬底，顺序地堆叠在衬底上的多个存储器组，每个存储器组包括至少一个存储器层，多个X译码器层，所述多个X译码器层中的至少一个是设置在所述多个存储器组中的每个相邻的两个存储器组之间，以及与所述多个X解码器层交替布置的多个Y译码器层，所述多个Y译码器层中的至少一个设置在每个相邻的两个存储器组之间的多个存储器组。

7. 发明申请

US20100202182A1 MEMORY DEVICES, SYSTEMS AND METHODS USING MULTIPLE 1/N PAGE ARRAYS AND MULTIPLE WRITE/READ CIRCUITS 审中-公开
标题翻译：使用多个1 / N页阵列和多个写/读电路的存储器件，系统和方法
公开(公告)号：US20100202182A1
公开(公告)日：2010-08-12
申请号：US12700882
申请日：2010-02-05
申请人： Sang Beom Kang , Ho Jung Kim , Chul Woo Park , Jung Min Lee , Hyun Ho Choi
发明人： Sang Beom Kang , Ho Jung Kim , Chul Woo Park , Jung Min Lee , Hyun Ho Choi
IPC分类号： G11C5/06 , G11C11/00 , G11C7/00 , G11C7/10
CPC分类号： G11C7/1078 , G11C7/1015 , G11C7/1051 , G11C7/18 , G11C2207/002 , G11C2207/107
摘要： A memory device architecture includes N arrays respectively for storing a 1/N of a page and N write/read circuits, where N is a natural number, respectively for writing or reading a 1/N of the page to/from each of the N arrays.
摘要翻译：存储器设备架构包括分别用于存储页面的1 / N和N个写入/读取电路的N个阵列，其中N是自然数，用于分别从/从N中的每个N写入或读取页面的1 / N 阵列

8. 发明申请

US20100172172A1 SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM INCLUDING THE SAME, AND VOLTAGE SUPPLY METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件，包括其的半导体系统和半导体器件的电压供应方法
公开(公告)号：US20100172172A1
公开(公告)日：2010-07-08
申请号：US12652209
申请日：2010-01-05
申请人： Ho Jung KIM , Chul Woo PARK , Sang Beom KANG , Jung Min LEE , Hyun Ho CHOI
发明人： Ho Jung KIM , Chul Woo PARK , Sang Beom KANG , Jung Min LEE , Hyun Ho CHOI
IPC分类号： G11C11/00 , G11C8/00 , G11C5/14
CPC分类号： G11C8/08 , G11C8/14
摘要： A semiconductor device, a semiconductor system including the same, and a voltage supply method of the semiconductor device are provided. The semiconductor device includes at least two semiconductor memory devices and a voltage supply controller configured to selectively supply a voltage to each of the at least two semiconductor memory devices.
摘要翻译：提供半导体器件，包括该半导体器件的半导体系统和半导体器件的电压供给方法。半导体器件包括至少两个半导体存储器件和被配置为选择性地向至少两个半导体存储器件中的每一个提供电压的电压供给控制器。

9. 发明申请

US20090296461A1 Memory Devices and Related Data Storage Devices and Systems Including the Same 审中-公开
标题翻译：内存设备及相关数据存储设备和系统包括其中
公开(公告)号：US20090296461A1
公开(公告)日：2009-12-03
申请号：US12471630
申请日：2009-05-26
申请人： Sang Beom Kang , Hyoung Seub Rhie
发明人： Sang Beom Kang , Hyoung Seub Rhie
IPC分类号： G11C11/14 , H01L29/82
CPC分类号： H01L27/228 , G11C11/16 , G11C11/1659 , G11C11/1675 , G11C19/0841
摘要： Memory devices that include a semiconductor substrate defining a data storage area and a peripheral circuit area. A first magnetic memory device is provided in the peripheral area of the semiconductor substrate and is configured to exchange data signals externally. A second magnetic memory device is provided in the data storage area of the semiconductor substrate and is configured to exchange the data signals with the first magnetic memory device. Each portion of the first magnetic memory device and a portion of the second magnetic memory device include a magnetic tunnel junction structure having at least one magnetic layer. Related data storage devices and systems are also provided.
摘要翻译：包括限定数据存储区域和外围电路区域的半导体衬底的存储器件。第一磁存储器件设置在半导体衬底的外围区域中，并被配置为从外部交换数据信号。第二磁存储器件设置在半导体衬底的数据存储区域中，并被配置为与第一磁存储器件交换数据信号。第一磁存储器件的每个部分和第二磁存储器件的一部分包括具有至少一个磁性层的磁性隧道结结构。还提供了相关的数据存储设备和系统。

10. 发明授权

US07586775B2 Nonvolatile memory device and related method of operation 有权
标题翻译：非易失存储器件及相关操作方法
公开(公告)号：US07586775B2
公开(公告)日：2009-09-08
申请号：US11850130
申请日：2007-09-05
申请人： Sang-beom Kang , Yong-jin Yoon , Qi Wang
发明人： Sang-beom Kang , Yong-jin Yoon , Qi Wang
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/009
摘要： A nonvolatile memory device comprises a first voltage generation unit, a second voltage generation unit, a first circuit block, and a discharge unit. The first voltage generation unit generates a first voltage with a first magnitude. The second voltage generation unit generates a second voltage with a second magnitude greater than the first magnitude. The first circuit block selectively receives the first voltage or the second voltage through an input node. The discharge unit discharges the input node between a time point where the input node has been charged with the second voltage and a time point where the input node receives the first voltage.
摘要翻译：非易失性存储器件包括第一电压产生单元，第二电压产生单元，第一电路块和放电单元。第一电压产生单元产生具有第一量值的第一电压。第二电压产生单元产生具有大于第一幅值的第二幅度的第二电压。第一电路块通过输入节点选择性地接收第一电压或第二电压。放电单元在输入节点已经被充电的时间点与第二电压之间和输入节点接收到第一电压的时间点之间对输入节点进行放电。

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