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1. 发明申请

US20080284504A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20080284504A1
公开(公告)日：2008-11-20
申请号：US12140351
申请日：2008-06-17
申请人： Makoto Hirota , Hidekazu Kikuchi , Sampei Miyamoto
发明人： Makoto Hirota , Hidekazu Kikuchi , Sampei Miyamoto
IPC分类号： G05F3/16
CPC分类号： H03K19/0016
摘要： This device has a first circuit including a first field effect transistor and a second circuit coupled to a source of the first electric field transistor. The second circuit applies a first source bias voltage, which does not reversely bias between a source and a body of the first field effect transistor, to the first field effect transistor during the operation mode of the first circuit, and applies a second source bias voltage, which reversely biases between the source and the body of the first field effect transistor, to the first field effect transistor during the standby mode of the first circuit. During the standby mode of the first circuit, the leakage current that flows through the first FET is reduced by means of the reverse bias effect produced by applying the second source bias voltage to the source of the first FET.
摘要翻译：该器件具有包括耦合到第一电场晶体管的源极的第一场效应晶体管和第二电路的第一电路。第二电路在第一电路的操作模式期间施加第一源极偏置电压，其不在第一场效应晶体管的源极和本体之间反向偏置到第一场效应晶体管，并施加第二源极偏置电压，其在第一电路的待机模式期间将第一场效应晶体管的源极和主体之间的偏置反向偏移到第一场效应晶体管。在第一电路的待机模式期间，通过将第二源偏置电压施加到第一FET的源而产生的反向偏置效应，流过第一FET的漏电流减小。

2. 发明授权

US6134153A Bi-directional data bus scheme with optimized read and write characters 有权
标题翻译：具有优化读写字符的双向数据总线方案
公开(公告)号：US6134153A
公开(公告)日：2000-10-17
申请号：US364181
申请日：1999-07-29
申请人： Valerie Lines , Cynthia Mar , Xiao Luo , Sampei Miyamoto
发明人： Valerie Lines , Cynthia Mar , Xiao Luo , Sampei Miyamoto
IPC分类号： G11C7/10 , G11C7/00 , G11C8/00
CPC分类号： G11C7/1051 , G11C7/1048
摘要： A bi-directional global data bus scheme for use in a random access memory which optimizes the performance of the data path for read and write operations while offering a uniform read and write frequency to the external processor or controller is presented. The system makes use of a dual local data bus structure which allows the column address to change on every clock cycle since the two parallel local data paths are activated on alternate clock cycles and therefore operate at half the nominal operating frequency. For the read operation, the global data buses operate differentially at the nominal operating frequency. For the write operation, the global data buses operate at half the nominal operating frequency with each global data bus of a complementary data bus pair being dedicated to either one or the other local data paths for every other clock cycle. By implementing this scheme internally, a uniform read or write operating frequency is seen by the microprocessor, thereby simplifying its interface with the memory.
摘要翻译：提供了一种用于随机存取存储器的双向全局数据总线方案，其优化用于读取和写入操作的数据路径的性能，同时向外部处理器或控制器提供均匀的读取和写入频率。该系统利用双局部数据总线结构，其允许列地址在每个时钟周期上改变，因为两个并行的本地数据路径在交替时钟周期上被激活，因此以标称工作频率的一半工作。对于读操作，全局数据总线在标称工作频率下差分工作。对于写入操作，全局数据总线以额定工作频率的一半工作，互补数据总线对的每个全局数据总线专用于每隔一个时钟周期的一个或另一个本地数据路径。通过内部实现该方案，微处理器可以看到均匀的读或写操作频率，从而简化了与存储器的接口。

3. 发明授权

US5850362A Semiconductor memory device employing an improved layout of sense amplifiers 失效
标题翻译：采用改进的读出放大器布局的半导体存储器件
公开(公告)号：US5850362A
公开(公告)日：1998-12-15
申请号：US619418
申请日：1996-03-21
申请人： Shinzo Sakuma , Sampei Miyamoto
发明人： Shinzo Sakuma , Sampei Miyamoto
IPC分类号： G11C11/409 , G11C5/06 , G11C7/00 , G11C11/401 , G11C11/4091 , G11C11/4097 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： G11C11/4097 , G11C11/4091
摘要： A memory device according to the invention has a first pair of bit lines, having first and second bit lines, coupled to a first memory cell which cause a first potential difference between the first and second bit lines; a second pair of bit lines, having third and fourth bit lines, coupled to a second memory cell which causes a second potential difference between the third and fourth bit lines; a first sense amplifier having first and second transistors each of which is a first conductivity type, the gate electrode of said first transistor being connected to said first bit line, the first electrode of the first transistor being connected to the second bit line, the gate electrode of the second transistor being connected to the second bit line, the first electrode of the second transistor being connected to the first bit line; a second sense amplifier having third and fourth transistors each of which is the first conductivity type, the gate electrode of the third transistor being connected to the third bit line, the first electrode of the third transistor being connected to the fourth bit line, the gate electrode of the fourth transistor being connected to the fourth bit line, the first electrode of the fourth transistor being connected to the third bit line; and the second electrodes of said first, second, third and fourth transistors constituting a first common diffusion region formed in a first area of the major surface.
摘要翻译：根据本发明的存储器件具有第一对位线，其具有第一和第二位线，耦合到第一存储器单元，该第一存储器单元引起第一和第二位线之间的第一电位差; 具有第三和第四位线的第二对位线，耦合到第二存储器单元，所述第二存储单元引起所述第三和第四位线之间的第二电位差; 具有第一和第二晶体管的第一感测放大器，每个第一和第二晶体管都是第一导电类型，所述第一晶体管的栅电极连接到所述第一位线，第一晶体管的第一电极连接到第二位线，栅极第二晶体管的电极连接到第二位线，第二晶体管的第一电极连接到第一位线; 具有第三和第四晶体管的第二感测放大器，每个第三和第四晶体管是第一导电类型，第三晶体管的栅电极连接到第三位线，第三晶体管的第一电极连接到第四位线，栅极第四晶体管的电极连接到第四位线，第四晶体管的第一电极连接到第三位线; 并且所述第一，第二，第三和第四晶体管的第二电极构成形成在主表面的第一区域中的第一公共扩散区域。

4. 发明授权

US5452260A Semiconductor memory circuit 失效
标题翻译：半导体存储电路
公开(公告)号：US5452260A
公开(公告)日：1995-09-19
申请号：US215487
申请日：1994-03-21
申请人： Katsuaki Matsui , Sampei Miyamoto , Tamihiro Ishimura
发明人： Katsuaki Matsui , Sampei Miyamoto , Tamihiro Ishimura
IPC分类号： G11C11/413 , G11C8/10 , G11C8/12 , G11C11/401 , G11C11/407 , G11C11/408 , G11C8/00
CPC分类号： G11C8/12 , G11C8/10
摘要： A semiconductor memory circuit selects one memory cell group in response to an address signal having block selection information, first and second significant bit information. First, to third memory cell blocks respectively have memory cell groups each including memory cells. First, to third decoder groups respectively have first decoders each coupled to one memory cell group in the first memory cell block, second decoders each coupled to one memory cell group in the second memory cell block, and third decoders each coupled to one memory cell group in the third memory cell block. First and second logic circuits respectively output a first common block selection signal with respect to the first and second memory cell blocks in response to the block selection information of the address signal, and a second common block selection signal with respect to the second and third memory cell blocks in response to the block selection information of the address signal. Third and fourth logic circuits respectively, in response to the second and first significant information, apply first common decode signals to the first and second decoder groups upon the first common block selection signal being outputted, and a plurality of second common decode signals to the second and third decoder groups upon the second common block selection signal being outputted. In response to the first and second common decode signals, a second decoder in the second decoder group is activated to select one memory cell group in the second memory cell block.
摘要翻译：半导体存储器电路响应具有块选择信息的地址信号，第一和第二有效位信息来选择一个存储单元组。首先，对第三存储单元块分别具有各自包含存储单元的存储单元组。首先，第三解码器组分别具有耦合到第一存储器单元块中的一个存储单元组的第一解码器，每个耦合到第二存储单元块中的一个存储单元组的第二解码器，以及每个耦合到一个存储单元组的第三解码器在第三个存储单元块中。第一和第二逻辑电路响应于地址信号的块选择信息分别输出关于第一和第二存储单元块的第一公共块选择信号，以及相对于第二和第三存储器的第二公共块选择信号响应于地址信号的块选择信息的单元块。第三和第四逻辑电路分别响应于第二和第一有效信息，在第一公共块选择信号被输出时，将第一公共解码信号应用于第一和第二解码器组，并将多个第二公共解码信号施加到第二公共解码信号第三解码器组输出第二公共块选择信号。响应于第一和第二公共解码信号，第二解码器组中的第二解码器被激活以选择第二存储器单元块中的一个存储器单元组。

5. 发明授权

US5363331A Semiconductor memory with column line control circuits for protection against broken column lines 失效
标题翻译：具有列线控制电路的半导体存储器，用于防止断线损坏
公开(公告)号：US5363331A
公开(公告)日：1994-11-08
申请号：US994674
申请日：1992-12-22
申请人： Katsuaki Matsui , Sampei Miyamoto
发明人： Katsuaki Matsui , Sampei Miyamoto
IPC分类号： G11C7/12 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/04 , G11C7/02
CPC分类号： G11C29/70 , G11C7/12
摘要： A semiconductor memory device has plural memory cell blocks, each including memory cells storing data therein. A data bus and switching circuits transfer data from the memory cells to the data bus in response to a first logic level signal applied thereto. Column lines each have first and second ends. Each column line is connected to the corresponding switching circuit in each of the memory cell blocks. A column decoder, coupled to the first end of the column lines, provides the first logic level signal to one of the column lines upon the memory cell blocks being accessed. Potential setting circuits are coupled to the second end of the column lines, and preliminarily set the respective column lines to be in a predetermined potential so that each switching circuit is inactive prior to the column decoder providing the first logic level signal. All the memory cells in an array can be prevented from becoming inoperative even if a column line is broken.
摘要翻译：半导体存储器件具有多个存储单元块，每个存储单元块包括在其中存储数据的存储器单元。数据总线和开关电路响应于施加到其上的第一逻辑电平信号将数据从存储器单元传送到数据总线。列线各具有第一和第二端。每个列线连接到每个存储单元块中的相应的开关电路。耦合到列线的第一端的列解码器在访问存储器单元块时将第一逻辑电平信号提供给列线之一。电位设置电路耦合到列线的第二端，并且预先将各列线设置为预定电位，使得在列解码器提供第一逻辑电平信号之前每个开关电路不活动。阵列中的所有存储单元即使列线被破坏，也可以防止它们不起作用。

6. 发明申请

US20070121358A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20070121358A1
公开(公告)日：2007-05-31
申请号：US11557485
申请日：2006-11-07
申请人： Makoto HIROTA , Hidekazu KIKUCHI , Sampei MIYAMOTO
发明人： Makoto HIROTA , Hidekazu KIKUCHI , Sampei MIYAMOTO
IPC分类号： G11C19/08
CPC分类号： G11C11/417 , G11C5/148 , G11C7/065 , G11C11/413 , G11C2207/065
摘要： This device has a first circuit including a first field effect transistor and a second circuit coupled to a source of the first electric field transistor. The second circuit applies a first source bias voltage, which does not reversely bias between a source and a body of the first field effect transistor, to the first field effect transistor during the operation mode of the first circuit, and applies a second source bias voltage, which reversely biases between the source and the body of the first field effect transistor, to the first field effect transistor during the standby mode of the first circuit. During the standby mode of the first circuit, the leakage current that flows through the first FET is reduced by means of the reverse bias effect produced by applying the second source bias voltage to the source of the first FET.
摘要翻译：该器件具有包括耦合到第一电场晶体管的源极的第一场效应晶体管和第二电路的第一电路。第二电路在第一电路的操作模式期间施加第一源极偏置电压，其不在第一场效应晶体管的源极和本体之间反向偏置到第一场效应晶体管，并施加第二源偏置电压，其在第一电路的待机模式期间将第一场效应晶体管的源极和主体之间的偏置反向偏移到第一场效应晶体管。在第一电路的待机模式期间，通过将第二源偏置电压施加到第一FET的源而产生的反向偏置效应，流过第一FET的漏电流减小。

7. 发明授权

US5521869A Semiconductor memory with improved transfer gate drivers 失效
公开(公告)号：US5521869A
公开(公告)日：1996-05-28
申请号：US351117
申请日：1994-11-30
申请人： Tamihiro Ishimura , Sampei Miyamoto
发明人： Tamihiro Ishimura , Sampei Miyamoto
IPC分类号： G11C11/409 , G11C7/06 , G11C11/401 , G11C11/407 , H03K3/356 , H03K17/10 , H03K19/017 , H03K17/06
CPC分类号： G11C7/06 , H03K17/102 , H03K3/356017 , H03K3/356113
摘要： A semiconductor memory has a sense amplifier array shared by first and second memory cell arrays, which are selected by first and second selection signals. Interconnections between the sense amplifier array and the first memory cell array are controlled by a first transfer gate signal. When the first selection signal is inactive, the second selection signal is coupled through a first transfer gate driver to become the first transfer gate signal. When the first selection signal is active, the first transfer gate signal is decoupled from the second selection signal and driven to an elevated level.

8. 发明授权

US4843258A Drive circuit with a ring oscillator for a semiconductor device 失效
标题翻译：具有用于半导体器件的环形振荡器的驱动电路
公开(公告)号：US4843258A
公开(公告)日：1989-06-27
申请号：US226087
申请日：1988-07-29
申请人： Masahumi Miyawaki , Sampei Miyamoto , Tamihiro Ishimura
发明人： Masahumi Miyawaki , Sampei Miyamoto , Tamihiro Ishimura
IPC分类号： G05F3/24 , G11C11/407 , G11C11/413 , H02M3/07 , H03K3/03 , H03K3/354
CPC分类号： G05F3/24 , H03K3/0315 , H03K3/354
摘要： A drive circuit for driving a semiconductor device includes a reference voltage level generator for outputting a reference voltage level which is associated with an input voltage level from an external power source. Supplied with the reference level, a ring oscillator oscillates a frequency signal having a predetermined frequency. A drive voltage level generator responds to the reference level and the frequency signal for producing a drive voltage level which is constantly substantially equal to the reference level in synchronism with the frequency signal. The drive voltage level generator feeds power from the external power source to the semiconductor device at the drive level, thereby driving the semiconductor load circuit.
摘要翻译：用于驱动半导体器件的驱动电路包括用于输出与来自外部电源的输入电压电平相关联的参考电压电平的参考电压电平发生器。提供参考电平，环形振荡器振荡具有预定频率的频率信号。驱动电压电平发生器响应参考电平和频率信号，以产生与频率信号同步地恒定地基本上等于参考电平的驱动电压电平。驱动电压电平发生器将来自外部电源的功率从驱动电平提供给半导体器件，由此驱动半导体负载电路。

9. 发明授权

US5394368A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5394368A
公开(公告)日：1995-02-28
申请号：US50231
申请日：1993-06-21
申请人： Sampei Miyamoto
发明人： Sampei Miyamoto
IPC分类号： G11C29/00 , G11C11/407
CPC分类号： G11C29/78 , G11C29/848
摘要： A semiconductor memory device having a redundancy circuit having a large flexibility, wherein a plurality of fuse columns are operated by address signals.
摘要翻译： PCT No.PCT / JP91 / 01142 Sec。 371日期：1993年6月21日 102（e）日期1993年6月21日PCT 1991年8月28日PCT PCT。第WO93 / 05512号公报日期1993年3月18日。一种具有灵活性大的冗余电路的半导体存储器件，其中多个熔丝列由地址信号操作。

10. 发明授权

US5982674A Bi-directional data bus scheme with optimized read and write characters 有权
公开(公告)号：US5982674A
公开(公告)日：1999-11-09
申请号：US163341
申请日：1998-09-30
申请人： Valeria Lines , Cynthia Mar , Xiao Luo , Sampei Miyamoto
发明人： Valeria Lines , Cynthia Mar , Xiao Luo , Sampei Miyamoto
IPC分类号： G11C7/10 , G11C7/00 , G11C8/00
CPC分类号： G11C7/1051 , G11C7/1048
摘要： A bi-directional global data bus scheme for use in a random access memory which optimizes the performance of the data path for read and write operations while offering a uniform read and write frequency to the external processor or controller is presented. The system makes use of a dual local data bus structure which allows the column address to change on every clock cycle since the two parallel local data paths are activated on alternate clock cycles and therefore operate at half the nominal operating frequency. For the read operation, the global data buses operate differentially at the nominal operating frequency. For the write operation, the global data buses operate at half the nominal operating frequency with each global data bus of a complementary data bus pair being dedicated to either one or the other local data paths for every other clock cycle. By implementing this scheme internally, a uniform read or write operating frequency is seen by the microprocessor, thereby simplifying its interface with the memory.

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