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1. 发明申请

US20130307611A1 MULTI-CHIP PACKAGE AND OPERATING METHOD THEREOF 有权
标题翻译：多芯片封装及其操作方法
公开(公告)号：US20130307611A1
公开(公告)日：2013-11-21
申请号：US13572086
申请日：2012-08-10
申请人： Won-Kyung KANG , Sam-Kyu WON
发明人： Won-Kyung KANG , Sam-Kyu WON
IPC分类号： H01L25/16 , H03H11/02 , H01L23/48
CPC分类号： G11C5/14
摘要： A multi-chip package includes first and second semiconductor chips each configured to perform first and second operations having different current consumptions. The first and second semiconductor chips perform the first operation in response to an enable control signal transmitted from one of the first and second semiconductor chips to the other and transmitted from the other back to the one.
摘要翻译：多芯片封装包括第一和第二半导体芯片，每个半导体芯片被配置为执行具有不同电流消耗的第一和第二操作。第一和第二半导体芯片响应于从第一和第二半导体芯片中的一个发送到另一个半导体芯片的使能控制信号并且从另一个发送到另一个半导体芯片来执行第一操作。

2. 发明申请

US20110122707A1 PAGE BUFFER CIRCUIT, NONVOLATILE MEMORY DEVICE INCLUDING THE PAGE BUFFER CIRCUIT, AND METHOD OF OPERATING THE NONVOLATILE MEMORY DEVICE 有权
标题翻译：页面缓冲器电路，包括页面缓冲器电路的非易失性存储器件以及操作非易失性存储器件的方法
公开(公告)号：US20110122707A1
公开(公告)日：2011-05-26
申请号：US13011316
申请日：2011-01-21
申请人： Chang Won Yang , Cheul Hee Koo , Sam Kyu Won
发明人： Chang Won Yang , Cheul Hee Koo , Sam Kyu Won
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/24 , G11C7/12 , G11C16/0483 , G11C16/10 , G11C16/3454 , G11C16/3459
摘要： A page buffer circuit comprises a bit line selection unit, a latch unit, and a bit line control unit. The bit line selection unit is configured to select a bit line coupled to memory cells. The latch unit comprises a plurality of latch circuits. The plurality of latch circuits is coupled to a sense node and configured to latch data to be programmed into the memory cells or store data from the memory cells. The bit line control unit is coupled to the sense node and configured to temporarily charge a voltage of the selected bit line in response to charge and transfer control signals or transfer the charged voltage to the selected bit line.
摘要翻译：页面缓冲电路包括位线选择单元，锁存单元和位线控制单元。位线选择单元被配置为选择耦合到存储器单元的位线。锁存单元包括多个锁存电路。多个锁存电路耦合到感测节点并且被配置为将要编程的数据锁存到存储器单元中或存储来自存储器单元的数据。位线控制单元耦合到感测节点并且被配置为响应于充电和传送控制信号临时对所选位线的电压充电或将充电电压传送到所选择的位线。

3. 发明授权

US07808840B2 Method of operating a non-volatile memory device 有权
标题翻译：操作非易失性存储器件的方法
公开(公告)号：US07808840B2
公开(公告)日：2010-10-05
申请号：US12163947
申请日：2008-06-27
申请人： Kwang Ho Baek , Sam Kyu Won , Jae Won Cha
发明人： Kwang Ho Baek , Sam Kyu Won , Jae Won Cha
IPC分类号： G11C7/10
CPC分类号： G11C11/5642 , G11C2211/5621
摘要： In a method of operating a non-volatile memory device, a bit line is precharged to a positive voltage, which is input through a common source line of cell strings of memory cells, according to a degree in which a selected memory cell has been programmed. Data according to a voltage level of a sensing node, which is changed according to a level of the voltage of the bit line, is stored in a first latch of a page buffer. The data stored in the first latch is transferred to a second latch through the sensing node.
摘要翻译：在操作非易失性存储器件的方法中，根据所选择的存储器单元已被编程的程度，位线被预充电到正电压，该正电压通过存储器单元的单元串的公共源极线输入。根据位线的电压的电平而改变的感测节点的电压电平的数据被存储在页缓冲器的第一锁存器中。存储在第一锁存器中的数据通过感测节点传送到第二锁存器。

4. 发明授权

US07800955B2 Programming method of a non-volatile memory device 有权
标题翻译：非易失性存储器件的编程方法
公开(公告)号：US07800955B2
公开(公告)日：2010-09-21
申请号：US12134943
申请日：2008-06-06
申请人： Sam Kyu Won , Jae Won Cha , Kwang Ho Baek
发明人： Sam Kyu Won , Jae Won Cha , Kwang Ho Baek
IPC分类号： G11C11/34
CPC分类号： G11C16/3454 , G11C8/08 , G11C16/0483 , G11C16/08 , G11C16/30
摘要： In a programming method of a non-volatile memory device, a program operation is performed by applying a program voltage to a selected word line and a first pass voltage to unselected word lines. The first pass voltage shifts to a second pass voltage having a level lower than that of the first pass voltage. A verify operation is performed by applying a verify voltage to the selected word line. The verify voltage has a level lower than that of the second pass voltage.
摘要翻译：在非易失性存储器件的编程方法中，通过将程序电压施加到所选择的字线并将第一通过电压施加到未选择的字线来执行编程操作。第一通过电压移动到具有低于第一通过电压的电平的第二通过电压。通过对所选择的字线应用验证电压来执行验证操作。验证电压的电平低于第二通过电压的电平。

5. 发明授权

US07787299B2 Semiconductor memory device and erase method in the same 失效
标题翻译：半导体存储器件和擦除方法相同
公开(公告)号：US07787299B2
公开(公告)日：2010-08-31
申请号：US12136738
申请日：2008-06-10
申请人： Sam Kyu Won , Jae Won Cha , In Ho Kang , Kwang Ho Baek
发明人： Sam Kyu Won , Jae Won Cha , In Ho Kang , Kwang Ho Baek
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/3404 , G11C16/344
摘要： A semiconductor memory device and an erase method in the same are disclosed. The semiconductor memory device includes a memory cell array configured to have a cell string in which memory cells are coupled, a block switch configured to switch a global word line and a word line of the memory cell array, a block decoder configured to control the block switch, and a recycle switch configured to use an erase voltage charged in a P-well of the memory cell array as a supply voltage of the block decoder.
摘要翻译：公开了一种半导体存储器件及其擦除方法。半导体存储器件包括配置成具有存储单元耦合的单元串的存储单元阵列，被配置为切换存储单元阵列的全局字线和字线的块开关，被配置为控制该块的块解码器开关和被配置为使用充电在存储单元阵列的P阱中的擦除电压作为块解码器的电源电压的再循环开关。

6. 发明申请

US20090231919A1 SEMICONDUCTOR MEMORY DEVICE AND ERASE METHOD IN THE SAME 失效
标题翻译：半导体存储器件及其擦除方法
公开(公告)号：US20090231919A1
公开(公告)日：2009-09-17
申请号：US12136738
申请日：2008-06-10
申请人： Sam Kyu WON , Jae Won Cha , In Ho Kang , Kwang Ho Baek
发明人： Sam Kyu WON , Jae Won Cha , In Ho Kang , Kwang Ho Baek
IPC分类号： G11C16/06
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/3404 , G11C16/344
摘要： A semiconductor memory device and an erase method in the same are disclosed. The semiconductor memory device includes a memory cell array configured to have a cell string in which memory cells are coupled, a block switch configured to switch a global word line and a word line of the memory cell array, a block decoder configured to control the block switch, and a recycle switch configured to use an erase voltage charged in a P-well of the memory cell array as a supply voltage of the block decoder.
摘要翻译：公开了一种半导体存储器件及其擦除方法。半导体存储器件包括配置成具有存储单元耦合的单元串的存储单元阵列，被配置为切换存储单元阵列的全局字线和字线的块开关，被配置为控制该块的块解码器开关和被配置为使用充电在存储单元阵列的P阱中的擦除电压作为块解码器的电源电压的再循环开关。

7. 发明申请

US20090185419A1 PAGE BUFFER CIRCUIT WITH REDUCED SIZE AND METHODS FOR READING AND PROGRAMMING DATA WITH THE SAME 有权
标题翻译：具有减小尺寸的页面缓冲器电路和用于读取和编程数据的方法
公开(公告)号：US20090185419A1
公开(公告)日：2009-07-23
申请号：US12409400
申请日：2009-03-23
申请人： Jin Yong Seong , Sam Kyu Won
发明人： Jin Yong Seong , Sam Kyu Won
IPC分类号： G11C16/00 , G11C16/06
CPC分类号： G11C16/26 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/12 , G11C16/3459 , G11C2211/5642
摘要： A page buffer circuit with reduced size and methods for reading and programming data is provided. In the reading operation, the page buffer circuit reads out a data bit by alternatively using a higher bit register or a lower bit register regardless of whether the data bit read from the multi-level cell is a higher bit or a lower bit, thereby reducing the circuit area and improves the performance of operation.
摘要翻译：提供了一种缩小尺寸的页面缓冲电路和用于读取和编程数据的方法。在读取操作中，页缓冲器电路通过交替地使用较高位寄存器或低位寄存器读出数据位，而不管从多级单元读取的数据位是高位还是低位，从而减少电路面积提高了运行性能。

8. 发明授权

US07515477B2 Non-volatile memory device and method of programming the same 有权
标题翻译：非易失性存储器件及其编程方法相同
公开(公告)号：US07515477B2
公开(公告)日：2009-04-07
申请号：US11751586
申请日：2007-05-21
申请人： Jae Won Cha , Sam Kyu Won , Kwang Ho Baek
发明人： Jae Won Cha , Sam Kyu Won , Kwang Ho Baek
IPC分类号： G11C16/06
CPC分类号： G11C16/24 , G11C16/0483 , G11C16/12
摘要： A non-volatile memory device comprises an even bit line and an odd bit line contacting to a memory cell array. A register unit includes a first register and a second register for temporarily storing data. A detecting node detects a voltage level of the specific bit line or the specific register which is connected to the bit lines and the registers. A selecting unit of the bit line includes a first variable voltage input terminal and a second variable voltage input terminal. The first variable voltage input terminal applies a first variable voltage of a specific voltage level to the even bit line in response to an even discharge signal. The second variable voltage input terminal applies a second variable voltage of a specific voltage level to the odd bit line in response to an odd discharge signal.
摘要翻译：非易失性存储器件包括偶数位线和与存储器单元阵列接触的奇数位线。寄存器单元包括用于临时存储数据的第一寄存器和第二寄存器。检测节点检测连接到位线和寄存器的特定位线或特定寄存器的电压电平。位线的选择单元包括第一可变电压输入端和第二可变电压输入端。第一可变电压输入端子响应于均匀放电信号向偶数位线施加特定电压电平的第一可变电压。第二可变电压输入端子响应于奇数放电信号向奇数位线施加特定电压电平的第二可变电压。

9. 发明申请

US20090040830A1 BLOCK DECODER AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
标题翻译：块解码器和半导体存储器件，包括它们
公开(公告)号：US20090040830A1
公开(公告)日：2009-02-12
申请号：US12163905
申请日：2008-06-27
申请人： Kwang Ho BAEK , Sam Kyu WON , Jae Won CHA
发明人： Kwang Ho BAEK , Sam Kyu WON , Jae Won CHA
IPC分类号： G11C16/04 , G11C7/00 , G11C8/00
CPC分类号： G11C16/08 , G11C11/10 , G11C11/12 , G11C11/14 , G11C16/0483
摘要： A semiconductor memory device can improve electrical properties by prohibiting a leakage current, which flows through a memory cell, in such a way as to turn off a drain select transistor, a source select transistor and a side transistor of an unselected memory cell block when the semiconductor memory device operates. The semiconductor memory device includes a memory cell block in which a plurality of memory cells, drain and source select transistors, and side word line transistors are connected in a string structure, a block decoder for outputting a block select signal in response to predecoded address signals and controlling the drain and source select transistors and the side word line transistors, and a block switch for connecting a global word line to word lines of the memory cell block in response to the block select signal.
摘要翻译：半导体存储器件可以通过阻止流过存储单元的泄漏电流来改善电性能，以便当非选择存储单元块的漏极选择晶体管，源选择晶体管和侧晶体管截止时半导体存储器件工作。半导体存储器件包括存储单元块，其中多个存储器单元，漏极和源极选择晶体管和侧面字线晶体管串联连接在一起;块解码器，用于响应于预解码的地址信号输出块选择信号以及控制漏极和源极选择晶体管和侧面字线晶体管，以及用于响应于块选择信号将全局字线连接到存储器单元块的字线的块开关。

10. 发明申请

US20080084772A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080084772A1
公开(公告)日：2008-04-10
申请号：US11617200
申请日：2006-12-28
申请人： Sam Kyu Won
发明人： Sam Kyu Won
IPC分类号： G11C5/14 , G11C29/00 , G11C7/00
CPC分类号： G11C29/02 , G11C5/145 , G11C29/021
摘要： A semiconductor memory device includes a high voltage generator for generating a high voltage and applying the generated high voltage to a memory unit, a converter for converting an output voltage of the high voltage generator into a digital signal, and a mode selection unit for outputting an output of the converter or an output of the memory unit through an I/O terminal selectively.
摘要翻译：半导体存储器件包括用于产生高电压并将所产生的高电压施加到存储器单元的高压发生器，用于将高电压发生器的输出电压转换为数字信号的转换器，以及用于输出选择性地通过I / O端子输出转换器或存储器单元的输出。

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