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    • 2. 发明申请
    • FACILITATING GROUP ACCESS CONTROL TO DATA OBJECTS IN PEER- TO-PEER OVERLAY NETWORKS
    • 实现对对等网络数据对象的访问控制
    • WO2013003783A1
    • 2013-01-03
    • PCT/US2012/045060
    • 2012-06-29
    • QUALCOMM INCORPORATEDMAO, YinianNARAYANAN, VidyaSWAMINATHAN, Ashwin
    • MAO, YinianNARAYANAN, VidyaSWAMINATHAN, Ashwin
    • H04L29/06
    • H04L67/1044H04L9/321H04L9/3247H04L9/3268H04L63/0823H04L63/104
    • Methods and apparatuses are provided for facilitating group access controls in peer-to-peer or other similar overlay networks. A group administrator may create a group in the overlay network and may assign peer-specific certificates to each member of the group for indicating membership in the group. A group member peer node can access data objects in the overlay network using its respective peer-specific certificate to authenticate itself as a group member. The authentication is performed by another peer node in the network. The validating peer node can authenticate that the group member is the rightful possessor of the peer-specific certificate using a public key associated with the peer node to which the peer-specific certificate was issued. The validating peer node can also validate that the peer-specific certificate was properly issued to the group member using a public key of the apparatus that issued the peer-specific certificate.
    • 提供了用于促进对等或其他类似覆盖网络中的组访问控制的方法和装置。 组管理员可以在覆盖网络中创建一个组,并且可以向组中的每个成员分配对等体特定的证书以指示组中的成员资格。 组成员对等节点可以使用其各自的特定于对等体的证书来访问覆盖网络中的数据对象,以将其自身认证为组成员。 该认证由网络中的另一个对等节点执行。 验证对等节点可以使用与发布对等特定证书的对等节点相关联的公钥来认证组成员是对等特定证书的合法拥有者。 验证对等节点还可以使用发布对等体特定证书的设备的公钥来验证对等特定证书是否已正确发布给组成员。
    • 5. 发明申请
    • DELAY LINE THAT TRACKS SETUP TIME OF A LATCHING ELEMENT OVER PVT
    • 延迟线,跟踪PVT上的锁定元件的设置时间
    • WO2011034862A1
    • 2011-03-24
    • PCT/US2010/048822
    • 2010-09-14
    • QUALCOMM INCORPORATEDSWAMINATHAN, AshwinPEDRALI-NOY, Marzio
    • SWAMINATHAN, AshwinPEDRALI-NOY, Marzio
    • H03K3/037H03K3/356
    • H03K3/0375H03K3/356156
    • A latching element (124) latches incoming data (D(7:0)) into an integrated circuit (101). The latching element (for example, a latch or flip-flop) can be considered to include a data path portion (126), a clock path portion (127), and an ideal latching element (125). In one embodiment, an open-loop replica (118) of the data path portion (126) is disposed in a clock signal path between a clock input terminal (116) of the integrated circuit and a clock input lead (130) of the latching element. In a second embodiment, an additional replica (144) of the clock path portion is disposed in a data signal path between a data terminal (105) of the integrated circuit (101) and a data input lead (128) of the latching element. The replica circuits (118,144) help prevent changes in skew between a data path propagation time to the ideal latching element and clock path propagation time to the ideal latching element. Setup times remain substantially constant over PVT (process, supply voltage, temperature).
    • 锁存元件(124)将输入数据(D(7:0))锁存到集成电路(101)中。 锁存元件(例如,锁存器或触发器)可以被认为包括数据路径部分(126),时钟路径部分(127)和理想锁存元件(125)。 在一个实施例中,数据路径部分(126)的开环复制品(118)被布置在集成电路的时钟输入端(116)和时钟输入引线(130)之间的时钟信号路径中, 元件。 在第二实施例中,时钟路径部分的附加副本(144)被布置在集成电路(101)的数据终端(105)和锁存元件的数据输入引线(128)之间的数据信号路径中。 复制电路(118,144)有助于防止在理想锁存元件的数据路径传播时间与理想锁存元件的时钟路径传播时间之间的偏差变化。 PVT(工艺,电源电压,温度)的设置时间基本保持不变。